Lines Matching refs:mes
85 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, in mes_v10_1_submit_pkt_and_poll_completion() argument
91 struct amdgpu_device *adev = mes->adev; in mes_v10_1_submit_pkt_and_poll_completion()
92 struct amdgpu_ring *ring = &mes->ring; in mes_v10_1_submit_pkt_and_poll_completion()
128 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_add_hw_queue() argument
131 struct amdgpu_device *adev = mes->adev; in mes_v10_1_add_hw_queue()
161 mes->ring.fence_drv.gpu_addr; in mes_v10_1_add_hw_queue()
163 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_add_hw_queue()
165 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_add_hw_queue()
169 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_remove_hw_queue() argument
184 mes->ring.fence_drv.gpu_addr; in mes_v10_1_remove_hw_queue()
186 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_remove_hw_queue()
188 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_remove_hw_queue()
192 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes, in mes_v10_1_suspend_gang() argument
198 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes, in mes_v10_1_resume_gang() argument
204 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) in mes_v10_1_query_sched_status() argument
215 mes->ring.fence_drv.gpu_addr; in mes_v10_1_query_sched_status()
217 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_query_sched_status()
219 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_query_sched_status()
223 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) in mes_v10_1_set_hw_resources() argument
226 struct amdgpu_device *adev = mes->adev; in mes_v10_1_set_hw_resources()
235 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v10_1_set_hw_resources()
236 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v10_1_set_hw_resources()
239 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; in mes_v10_1_set_hw_resources()
241 mes->query_status_fence_gpu_addr; in mes_v10_1_set_hw_resources()
245 mes->compute_hqd_mask[i]; in mes_v10_1_set_hw_resources()
248 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; in mes_v10_1_set_hw_resources()
251 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; in mes_v10_1_set_hw_resources()
255 mes->agreegated_doorbells[i]; in mes_v10_1_set_hw_resources()
258 mes->ring.fence_drv.gpu_addr; in mes_v10_1_set_hw_resources()
260 ++mes->ring.fence_drv.sync_seq; in mes_v10_1_set_hw_resources()
262 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_set_hw_resources()
293 err = request_firmware(&adev->mes.fw, fw_name, adev->dev); in mes_v10_1_init_microcode()
297 err = amdgpu_ucode_validate(adev->mes.fw); in mes_v10_1_init_microcode()
299 release_firmware(adev->mes.fw); in mes_v10_1_init_microcode()
300 adev->mes.fw = NULL; in mes_v10_1_init_microcode()
304 mes_hdr = (const struct mes_firmware_header_v1_0 *)adev->mes.fw->data; in mes_v10_1_init_microcode()
305 adev->mes.ucode_fw_version = le32_to_cpu(mes_hdr->mes_ucode_version); in mes_v10_1_init_microcode()
306 adev->mes.ucode_fw_version = in mes_v10_1_init_microcode()
308 adev->mes.uc_start_addr = in mes_v10_1_init_microcode()
311 adev->mes.data_start_addr = in mes_v10_1_init_microcode()
318 info->fw = adev->mes.fw; in mes_v10_1_init_microcode()
325 info->fw = adev->mes.fw; in mes_v10_1_init_microcode()
336 release_firmware(adev->mes.fw); in mes_v10_1_free_microcode()
337 adev->mes.fw = NULL; in mes_v10_1_free_microcode()
348 adev->mes.fw->data; in mes_v10_1_allocate_ucode_buffer()
350 fw_data = (const __le32 *)(adev->mes.fw->data + in mes_v10_1_allocate_ucode_buffer()
356 &adev->mes.ucode_fw_obj, in mes_v10_1_allocate_ucode_buffer()
357 &adev->mes.ucode_fw_gpu_addr, in mes_v10_1_allocate_ucode_buffer()
358 (void **)&adev->mes.ucode_fw_ptr); in mes_v10_1_allocate_ucode_buffer()
364 memcpy(adev->mes.ucode_fw_ptr, fw_data, fw_size); in mes_v10_1_allocate_ucode_buffer()
366 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj); in mes_v10_1_allocate_ucode_buffer()
367 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj); in mes_v10_1_allocate_ucode_buffer()
380 adev->mes.fw->data; in mes_v10_1_allocate_ucode_data_buffer()
382 fw_data = (const __le32 *)(adev->mes.fw->data + in mes_v10_1_allocate_ucode_data_buffer()
388 &adev->mes.data_fw_obj, in mes_v10_1_allocate_ucode_data_buffer()
389 &adev->mes.data_fw_gpu_addr, in mes_v10_1_allocate_ucode_data_buffer()
390 (void **)&adev->mes.data_fw_ptr); in mes_v10_1_allocate_ucode_data_buffer()
396 memcpy(adev->mes.data_fw_ptr, fw_data, fw_size); in mes_v10_1_allocate_ucode_data_buffer()
398 amdgpu_bo_kunmap(adev->mes.data_fw_obj); in mes_v10_1_allocate_ucode_data_buffer()
399 amdgpu_bo_unreserve(adev->mes.data_fw_obj); in mes_v10_1_allocate_ucode_data_buffer()
406 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj, in mes_v10_1_free_ucode_buffers()
407 &adev->mes.data_fw_gpu_addr, in mes_v10_1_free_ucode_buffers()
408 (void **)&adev->mes.data_fw_ptr); in mes_v10_1_free_ucode_buffers()
410 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj, in mes_v10_1_free_ucode_buffers()
411 &adev->mes.ucode_fw_gpu_addr, in mes_v10_1_free_ucode_buffers()
412 (void **)&adev->mes.ucode_fw_ptr); in mes_v10_1_free_ucode_buffers()
426 (uint32_t)(adev->mes.uc_start_addr) >> 2); in mes_v10_1_enable()
454 if (!adev->mes.fw) in mes_v10_1_load_microcode()
477 (uint32_t)(adev->mes.uc_start_addr) >> 2); in mes_v10_1_load_microcode()
481 lower_32_bits(adev->mes.ucode_fw_gpu_addr)); in mes_v10_1_load_microcode()
483 upper_32_bits(adev->mes.ucode_fw_gpu_addr)); in mes_v10_1_load_microcode()
490 lower_32_bits(adev->mes.data_fw_gpu_addr)); in mes_v10_1_load_microcode()
492 upper_32_bits(adev->mes.data_fw_gpu_addr)); in mes_v10_1_load_microcode()
549 &adev->mes.eop_gpu_obj, in mes_v10_1_allocate_eop_buf()
550 &adev->mes.eop_gpu_addr, in mes_v10_1_allocate_eop_buf()
557 memset(eop, 0, adev->mes.eop_gpu_obj->tbo.base.size); in mes_v10_1_allocate_eop_buf()
559 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj); in mes_v10_1_allocate_eop_buf()
560 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj); in mes_v10_1_allocate_eop_buf()
569 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs); in mes_v10_1_allocate_mem_slots()
575 adev->mes.sch_ctx_gpu_addr = in mes_v10_1_allocate_mem_slots()
576 adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4); in mes_v10_1_allocate_mem_slots()
577 adev->mes.sch_ctx_ptr = in mes_v10_1_allocate_mem_slots()
578 (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs]; in mes_v10_1_allocate_mem_slots()
580 r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs); in mes_v10_1_allocate_mem_slots()
586 adev->mes.query_status_fence_gpu_addr = in mes_v10_1_allocate_mem_slots()
587 adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4); in mes_v10_1_allocate_mem_slots()
588 adev->mes.query_status_fence_ptr = in mes_v10_1_allocate_mem_slots()
589 (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs]; in mes_v10_1_allocate_mem_slots()
802 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
817 r = mes_v10_1_mqd_init(&adev->mes.ring); in mes_v10_1_queue_init()
826 mes_v10_1_queue_init_register(&adev->mes.ring); in mes_v10_1_queue_init()
836 ring = &adev->mes.ring; in mes_v10_1_ring_init()
847 ring->eop_gpu_addr = adev->mes.eop_gpu_addr; in mes_v10_1_ring_init()
858 struct amdgpu_ring *ring = &adev->mes.ring; in mes_v10_1_mqd_sw_init()
872 adev->mes.mqd_backup = kmalloc(mqd_size, GFP_KERNEL); in mes_v10_1_mqd_sw_init()
873 if (!adev->mes.mqd_backup) in mes_v10_1_mqd_sw_init()
886 adev->mes.adev = adev; in mes_v10_1_sw_init()
887 adev->mes.funcs = &mes_v10_1_funcs; in mes_v10_1_sw_init()
916 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); in mes_v10_1_sw_fini()
917 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); in mes_v10_1_sw_fini()
919 kfree(adev->mes.mqd_backup); in mes_v10_1_sw_fini()
921 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, in mes_v10_1_sw_fini()
922 &adev->mes.ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
923 &adev->mes.ring.mqd_ptr); in mes_v10_1_sw_fini()
925 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj, in mes_v10_1_sw_fini()
926 &adev->mes.eop_gpu_addr, in mes_v10_1_sw_fini()
953 r = mes_v10_1_set_hw_resources(&adev->mes); in mes_v10_1_hw_init()
957 r = mes_v10_1_query_sched_status(&adev->mes); in mes_v10_1_hw_init()