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Lines Matching refs:ih

53 	if (adev->irq.ih.ring_size) {  in navi10_ih_init_register_offset()
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
153 struct amdgpu_ih_ring *ih, in navi10_ih_toggle_ring_interrupts() argument
159 ih_regs = &ih->ih_regs; in navi10_ih_toggle_ring_interrupts()
164 if (ih == &adev->irq.ih) in navi10_ih_toggle_ring_interrupts()
175 ih->enabled = true; in navi10_ih_toggle_ring_interrupts()
180 ih->enabled = false; in navi10_ih_toggle_ring_interrupts()
181 ih->rptr = 0; in navi10_ih_toggle_ring_interrupts()
197 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in navi10_ih_toggle_interrupts() local
201 for (i = 0; i < ARRAY_SIZE(ih); i++) { in navi10_ih_toggle_interrupts()
202 if (ih[i]->ring_size) { in navi10_ih_toggle_interrupts()
203 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); in navi10_ih_toggle_interrupts()
212 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in navi10_ih_rb_cntl() argument
214 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl()
217 MC_SPACE, ih->use_bus_addr ? 1 : 4); in navi10_ih_rb_cntl()
235 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) in navi10_ih_doorbell_rptr() argument
239 if (ih->use_doorbell) { in navi10_ih_doorbell_rptr()
242 ih->doorbell_index); in navi10_ih_doorbell_rptr()
263 struct amdgpu_ih_ring *ih) in navi10_ih_enable_ring() argument
268 ih_regs = &ih->ih_regs; in navi10_ih_enable_ring()
271 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in navi10_ih_enable_ring()
272 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in navi10_ih_enable_ring()
275 tmp = navi10_ih_rb_cntl(ih, tmp); in navi10_ih_enable_ring()
276 if (ih == &adev->irq.ih) in navi10_ih_enable_ring()
278 if (ih == &adev->irq.ih1) { in navi10_ih_enable_ring()
292 if (ih == &adev->irq.ih) { in navi10_ih_enable_ring()
294 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in navi10_ih_enable_ring()
295 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in navi10_ih_enable_ring()
302 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); in navi10_ih_enable_ring()
320 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in navi10_ih_irq_init() local
334 if (ih[0]->use_bus_addr) { in navi10_ih_irq_init()
357 for (i = 0; i < ARRAY_SIZE(ih); i++) { in navi10_ih_irq_init()
358 if (ih[i]->ring_size) { in navi10_ih_irq_init()
359 ret = navi10_ih_enable_ring(adev, ih[i]); in navi10_ih_irq_init()
366 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in navi10_ih_irq_init()
367 ih[0]->doorbell_index); in navi10_ih_irq_init()
421 struct amdgpu_ih_ring *ih) in navi10_ih_get_wptr() argument
426 wptr = le32_to_cpu(*ih->wptr_cpu); in navi10_ih_get_wptr()
427 ih_regs = &ih->ih_regs; in navi10_ih_get_wptr()
441 tmp = (wptr + 32) & ih->ptr_mask; in navi10_ih_get_wptr()
444 wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
445 ih->rptr = tmp; in navi10_ih_get_wptr()
451 return (wptr & ih->ptr_mask); in navi10_ih_get_wptr()
462 struct amdgpu_ih_ring *ih) in navi10_ih_irq_rearm() argument
468 ih_regs = &ih->ih_regs; in navi10_ih_irq_rearm()
473 if ((v < ih->ring_size) && (v != ih->rptr)) in navi10_ih_irq_rearm()
474 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_irq_rearm()
489 struct amdgpu_ih_ring *ih) in navi10_ih_set_rptr() argument
493 if (ih->use_doorbell) { in navi10_ih_set_rptr()
495 *ih->rptr_cpu = ih->rptr; in navi10_ih_set_rptr()
496 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_set_rptr()
499 navi10_ih_irq_rearm(adev, ih); in navi10_ih_set_rptr()
501 ih_regs = &ih->ih_regs; in navi10_ih_set_rptr()
502 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in navi10_ih_set_rptr()
574 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); in navi10_ih_sw_init()
578 adev->irq.ih.use_doorbell = true; in navi10_ih_sw_init()
579 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; in navi10_ih_sw_init()