28 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
30 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \  argument
32 	 adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
33 	 WREG32(reg, value))
35 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \  argument
37 	 adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
38 	 RREG32(reg))
40 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
41 	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
43 					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
45 				~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
48 #define RREG32_SOC15(ip, inst, reg) \  argument
49 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
52 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)  argument
54 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
55 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
58 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
59 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_H…
61 #define WREG32_SOC15(ip, inst, reg, value) \  argument
62 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
65 #define WREG32_SOC15_IP(ip, reg, value) \  argument
66 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
68 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
69 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
72 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
73 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
76 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \  argument
80 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
89 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
93 					  inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
102 #define WREG32_RLC(reg, value) \  argument
103 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
105 #define WREG32_RLC_EX(prefix, reg, value) \  argument
114 			WREG32(r1, (reg | 0x80000000));	\
123 				pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);	\
125 			WREG32(reg, value); \
130 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
131 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
134 #define RREG32_RLC(reg) \  argument
135 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
137 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \  argument
138 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
140 #define RREG32_RLC_NO_KIQ(reg, hwip) \  argument
141 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
143 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
145 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
161 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
162 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
164 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
166 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
170 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
172 			uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
176 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
177 	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
178 			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
180 			      ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
183 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
184 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AM…
186 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
187 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…