494 	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
498 	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
502 	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
507 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v6_0_hw_init()
510 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v6_0_hw_init()
933 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v6_0_ring_emit_fence()
935 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_fence()
937 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_fence()
939 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_fence()
942 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_fence()
944 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_fence()
946 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_fence()
1001 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v6_0_ring_test_ring()
1034 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));  in uvd_v6_0_ring_emit_ib()
1037 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));  in uvd_v6_0_ring_emit_ib()
1039 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));  in uvd_v6_0_ring_emit_ib()
1041 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v6_0_ring_emit_ib()
1072 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_wreg()
1074 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_wreg()
1076 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_wreg()
1085 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_vm_flush()
1087 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_vm_flush()
1089 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));  in uvd_v6_0_ring_emit_vm_flush()
1091 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_vm_flush()
1100 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1102 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1104 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1106 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1108 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1119 		amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));  in uvd_v6_0_ring_insert_nop()