Lines Matching refs:fclks
1486 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; in dcn_bw_update_from_pplib() local
1492 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); in dcn_bw_update_from_pplib()
1497 res = verify_clock_values(&fclks); in dcn_bw_update_from_pplib()
1500 ASSERT(fclks.num_levels); in dcn_bw_update_from_pplib()
1503 vmid0p72_idx = fclks.num_levels - in dcn_bw_update_from_pplib()
1504 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); in dcn_bw_update_from_pplib()
1505 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); in dcn_bw_update_from_pplib()
1506 vmax0p9_idx = fclks.num_levels - 1; in dcn_bw_update_from_pplib()
1509 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; in dcn_bw_update_from_pplib()
1512 (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib()
1516 (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib()
1520 (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib()