Lines Matching defs:dc_debug_options

525 struct dc_debug_options {  struct
526 	bool native422_support;
527 	bool disable_dsc;
528 	enum visual_confirm visual_confirm;
529 	bool sanity_checks;
530 	bool max_disp_clk;
531 	bool surface_trace;
532 	bool timing_trace;
533 	bool clock_trace;
534 	bool validation_trace;
535 	bool bandwidth_calcs_trace;
536 	int max_downscale_src_width;
539 	bool disable_stutter;
540 	bool use_max_lb;
541 	enum dcc_option disable_dcc;
542 	enum pipe_split_policy pipe_split_policy;
543 	bool force_single_disp_pipe_split;
544 	bool voltage_align_fclk;
545 	bool disable_min_fclk;
547 	bool disable_dfs_bypass;
548 	bool disable_dpp_power_gate;
549 	bool disable_hubp_power_gate;
550 	bool disable_dsc_power_gate;
551 	int dsc_min_slice_height_override;
552 	int dsc_bpp_increment_div;
553 	bool disable_pplib_wm_range;
554 	enum wm_report_mode pplib_wm_report_mode;
555 	unsigned int min_disp_clk_khz;
556 	unsigned int min_dpp_clk_khz;
557 	int sr_exit_time_dpm0_ns;
558 	int sr_enter_plus_exit_time_dpm0_ns;
559 	int sr_exit_time_ns;
560 	int sr_enter_plus_exit_time_ns;
561 	int urgent_latency_ns;
562 	uint32_t underflow_assert_delay_us;
563 	int percent_of_ideal_drambw;
564 	int dram_clock_change_latency_ns;
565 	bool optimized_watermark;
566 	int always_scale;
567 	bool disable_pplib_clock_request;
568 	bool disable_clock_gate;
569 	bool disable_mem_low_power;
571 	bool pstate_enabled;
573 	bool disable_dmcu;
574 	bool disable_psr;
575 	bool force_abm_enable;
576 	bool disable_stereo_support;
577 	bool vsr_support;
578 	bool performance_trace;
579 	bool az_endpoint_mute_only;
580 	bool always_use_regamma;
581 	bool recovery_enabled;
582 	bool avoid_vbios_exec_table;
583 	bool scl_reset_length10;
584 	bool hdmi20_disable;
585 	bool skip_detection_link_training;
586 	uint32_t edid_read_retry_times;
587 	bool remove_disconnect_edp;
588 	unsigned int force_odm_combine; //bit vector based on otg inst
590 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
591 	bool disable_z9_mpc;
593 	unsigned int force_fclk_khz;
594 	bool enable_tri_buf;
595 	bool dmub_offload_enabled;
596 	bool dmcub_emulation;
598 	bool disable_idle_power_optimizations;
599 	unsigned int mall_size_override;
600 	unsigned int mall_additional_timer_percent;
601 	bool mall_error_as_fatal;
603 	bool dmub_command_table; /* for testing only */
604 	struct dc_bw_validation_profile bw_val_profile;
605 	bool disable_fec;
606 	bool disable_48mhz_pwrdwn;
610 	unsigned int force_min_dcfclk_mhz;
612 	int dwb_fi_phase;
614 	bool disable_timing_sync;
615 	bool cm_in_bypass;
616 	int force_clock_mode;/*every mode change.*/
641 	struct dc_debug_options debug;  argument