1038 		struct display_mode_lib *dml,  in calculate_wm_set_for_vlevel()  argument
1042 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;  in calculate_wm_set_for_vlevel()
1044 	ASSERT(vlevel < dml->soc.num_states);  in calculate_wm_set_for_vlevel()
1047 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;  in calculate_wm_set_for_vlevel()
1048 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;  in calculate_wm_set_for_vlevel()
1050 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;  in calculate_wm_set_for_vlevel()
1051 	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;  in calculate_wm_set_for_vlevel()
1052 	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;  in calculate_wm_set_for_vlevel()
1054 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1055 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) …  in calculate_wm_set_for_vlevel()
1056 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1057 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1058 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1059 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1060 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1061 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1062 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;  in calculate_wm_set_for_vlevel()
1111 	patch_bounding_box(dc, &context->bw_ctx.dml.soc);  in dcn21_calculate_wm()
1118 …pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_c…  in dcn21_calculate_wm()
1122 …		context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];  in dcn21_calculate_wm()
1123 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)  in dcn21_calculate_wm()
1125 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];  in dcn21_calculate_wm()
1131 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_…  in dcn21_calculate_wm()
1132 				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])  in dcn21_calculate_wm()
1134 							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];  in dcn21_calculate_wm()
1162 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_calculate_wm()
1167 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_calculate_wm()
1172 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_calculate_wm()
1178 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_calculate_wm()
1214 	context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =  in dcn21_fast_validate_bw()
1216 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_fast_validate_bw()
1218 	if (vlevel > context->bw_ctx.dml.soc.num_states) {  in dcn21_fast_validate_bw()
1226 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =  in dcn21_fast_validate_bw()
1228 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn21_fast_validate_bw()
1229 		if (vlevel > context->bw_ctx.dml.soc.num_states)  in dcn21_fast_validate_bw()
1238 		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;  in dcn21_fast_validate_bw()
1268 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {  in dcn21_fast_validate_bw()
1291 …	context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;  in dcn21_fast_validate_bw()
1294 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {  in dcn21_fast_validate_bw()
1316 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =  in dcn21_fast_validate_bw()
1375 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st…  in dcn21_validate_bandwidth_fp()
1649 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);  in update_bw_bounding_box()
2137 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);  in dcn21_resource_construct()