Lines Matching refs:dc
64 dc->ctx->logger
97 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
144 bool dcn30_set_input_transfer_func(struct dc *dc, in dcn30_set_input_transfer_func() argument
148 struct dce_hwseq *hws = dc->hwseq; in dcn30_set_input_transfer_func()
187 bool dcn30_set_output_transfer_func(struct dc *dc, in dcn30_set_output_transfer_func() argument
192 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
220 struct dc *dc, in dcn30_set_writeback() argument
230 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
231 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
235 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
243 struct dc *dc, in dcn30_update_writeback() argument
248 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
253 dcn30_set_writeback(dc, wb_info, context); in dcn30_update_writeback()
260 struct dc *dc, in dcn30_mmhubbub_warmup() argument
270 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
284 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
292 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
299 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
300 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
308 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
318 struct dc *dc, in dcn30_enable_writeback() argument
326 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
327 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
330 optc = dc->res_pool->timing_generators[dwb->otg_inst]; in dcn30_enable_writeback()
334 if (IS_DIAG_DC(dc->ctx->dce_environment)) { in dcn30_enable_writeback()
336 dcn30_mmhubbub_warmup(dc, 1, wb_info); in dcn30_enable_writeback()
339 dcn30_set_writeback(dc, wb_info, context); in dcn30_enable_writeback()
348 struct dc *dc, in dcn30_disable_writeback() argument
355 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
356 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; in dcn30_disable_writeback()
365 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); in dcn30_disable_writeback()
369 struct dc *dc, in dcn30_program_all_writeback_pipes_in_tree() argument
388 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
398 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { in dcn30_program_all_writeback_pipes_in_tree()
414 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
418 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
419 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; in dcn30_program_all_writeback_pipes_in_tree()
422 dc->hwss.update_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
425 dc->hwss.enable_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
429 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
434 void dcn30_init_hw(struct dc *dc) in dcn30_init_hw() argument
436 struct abm **abms = dc->res_pool->multiple_abms; in dcn30_init_hw()
437 struct dce_hwseq *hws = dc->hwseq; in dcn30_init_hw()
438 struct dc_bios *dcb = dc->ctx->dc_bios; in dcn30_init_hw()
439 struct resource_pool *res_pool = dc->res_pool; in dcn30_init_hw()
444 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn30_init_hw()
445 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn30_init_hw()
451 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()
457 if (!dc->debug.disable_clock_gate) { in dcn30_init_hw()
474 hws->funcs.bios_golden_init(dc); in dcn30_init_hw()
475 hws->funcs.disable_vga(dc->hwseq); in dcn30_init_hw()
478 if (dc->debug.enable_mem_low_power.bits.dmcu) { in dcn30_init_hw()
480 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in dcn30_init_hw()
486 if (dc->debug.enable_mem_low_power.bits.optc) { in dcn30_init_hw()
491 if (dc->ctx->dc_bios->fw_info_valid) { in dcn30_init_hw()
493 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; in dcn30_init_hw()
495 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn30_init_hw()
499 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, in dcn30_init_hw()
516 for (i = 0; i < dc->link_count; i++) { in dcn30_init_hw()
521 struct dc_link *link = dc->links[i]; in dcn30_init_hw()
537 if (dc->config.power_down_display_on_boot) { in dcn30_init_hw()
541 for (i = 0; i < dc->link_count; i++) { in dcn30_init_hw()
542 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) in dcn30_init_hw()
545 dp_retrieve_lttpr_cap(dc->links[i]); in dcn30_init_hw()
548 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in dcn30_init_hw()
552 if (dc->links[i]->link_enc->funcs->get_dig_frontend) { in dcn30_init_hw()
555 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( in dcn30_init_hw()
556 dc->links[i]->link_enc); in dcn30_init_hw()
560 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { in dcn30_init_hw()
561 if (fe == dc->res_pool->stream_enc[j]->id) { in dcn30_init_hw()
562 dc->res_pool->stream_enc[j]->funcs->dp_blank( in dcn30_init_hw()
563 dc->res_pool->stream_enc[j]); in dcn30_init_hw()
568 dp_receiver_power_ctrl(dc->links[i], false); in dcn30_init_hw()
574 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn30_init_hw()
582 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { in dcn30_init_hw()
583 hws->funcs.init_pipes(dc, dc->current_state); in dcn30_init_hw()
584 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) in dcn30_init_hw()
585 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn30_init_hw()
586 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); in dcn30_init_hw()
594 if (dc->config.power_down_display_on_boot) { in dcn30_init_hw()
598 get_edp_links(dc, edp_links, &edp_num); in dcn30_init_hw()
603 dc->hwss.edp_backlight_control && in dcn30_init_hw()
604 dc->hwss.power_down && in dcn30_init_hw()
605 dc->hwss.edp_power_control) { in dcn30_init_hw()
606 dc->hwss.edp_backlight_control(edp_link, false); in dcn30_init_hw()
607 dc->hwss.power_down(dc); in dcn30_init_hw()
608 dc->hwss.edp_power_control(edp_link, false); in dcn30_init_hw()
610 for (i = 0; i < dc->link_count; i++) { in dcn30_init_hw()
611 struct dc_link *link = dc->links[i]; in dcn30_init_hw()
615 dc->hwss.power_down) { in dcn30_init_hw()
616 dc->hwss.power_down(dc); in dcn30_init_hw()
630 for (i = 0; i < dc->link_count; i++) { in dcn30_init_hw()
631 struct dc_link *link = dc->links[i]; in dcn30_init_hw()
637 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_init_hw()
645 if (!dc->debug.disable_clock_gate) { in dcn30_init_hw()
654 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) in dcn30_init_hw()
655 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn30_init_hw()
657 if (dc->clk_mgr->funcs->notify_wm_ranges) in dcn30_init_hw()
658 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); in dcn30_init_hw()
660 if (dc->clk_mgr->funcs->set_hard_max_memclk) in dcn30_init_hw()
661 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); in dcn30_init_hw()
663 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) in dcn30_init_hw()
664 dc->res_pool->hubbub->funcs->force_pstate_change_control( in dcn30_init_hw()
665 dc->res_pool->hubbub, false, false); in dcn30_init_hw()
666 if (dc->res_pool->hubbub->funcs->init_crb) in dcn30_init_hw()
667 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn30_init_hw()
734 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) in dcn30_apply_idle_power_optimizations() argument
743 if (!dc->ctx->dmub_srv) in dcn30_apply_idle_power_optimizations()
747 if (dc->current_state) { in dcn30_apply_idle_power_optimizations()
751 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn30_apply_idle_power_optimizations()
752 if (dc->current_state->stream_status[i].plane_count) in dcn30_apply_idle_power_optimizations()
757 if (i == dc->current_state->stream_count) { in dcn30_apply_idle_power_optimizations()
764 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn30_apply_idle_power_optimizations()
765 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
770 stream = dc->current_state->streams[0]; in dcn30_apply_idle_power_optimizations()
771 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); in dcn30_apply_idle_power_optimizations()
788 if (dc->current_state->stream_count == 1 && in dcn30_apply_idle_power_optimizations()
790 dc->current_state->stream_status[0].plane_count == 1 && in dcn30_apply_idle_power_optimizations()
794 dc->hwss.does_plane_fit_in_mall && in dcn30_apply_idle_power_optimizations()
795 dc->hwss.does_plane_fit_in_mall(dc, plane, in dcn30_apply_idle_power_optimizations()
825 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; in dcn30_apply_idle_power_optimizations()
828 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), in dcn30_apply_idle_power_optimizations()
852 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), in dcn30_apply_idle_power_optimizations()
887 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn30_apply_idle_power_optimizations()
888 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
889 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
903 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal; in dcn30_apply_idle_power_optimizations()
905 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn30_apply_idle_power_optimizations()
906 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
923 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn30_apply_idle_power_optimizations()
924 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
925 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); in dcn30_apply_idle_power_optimizations()
930 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_att… in dcn30_does_plane_fit_in_mall() argument
935 unsigned int mall_size = dc->caps.mall_size_total; in dcn30_does_plane_fit_in_mall()
938 if (dc->debug.mall_size_override) in dcn30_does_plane_fit_in_mall()
939 mall_size = 1024 * 1024 * dc->debug.mall_size_override; in dcn30_does_plane_fit_in_mall()
942 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; in dcn30_does_plane_fit_in_mall()
964 void dcn30_hardware_release(struct dc *dc) in dcn30_hardware_release() argument
967 if (!dc->clk_mgr->clks.p_state_change_support && in dcn30_hardware_release()
968 dc->res_pool->hubbub->funcs->force_pstate_change_control) in dcn30_hardware_release()
969 dc->res_pool->hubbub->funcs->force_pstate_change_control( in dcn30_hardware_release()
970 dc->res_pool->hubbub, true, true); in dcn30_hardware_release()
973 void dcn30_set_disp_pattern_generator(const struct dc *dc, in dcn30_set_disp_pattern_generator() argument