1624 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;  in dcn301_update_bw_bounding_box()
1626 	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);  in dcn301_update_bw_bounding_box()
1633 		struct display_mode_lib *dml,  in calculate_wm_set_for_vlevel()  argument
1637 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;  in calculate_wm_set_for_vlevel()
1639 	ASSERT(vlevel < dml->soc.num_states);  in calculate_wm_set_for_vlevel()
1642 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;  in calculate_wm_set_for_vlevel()
1643 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;  in calculate_wm_set_for_vlevel()
1645 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;  in calculate_wm_set_for_vlevel()
1646 	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;  in calculate_wm_set_for_vlevel()
1647 	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;  in calculate_wm_set_for_vlevel()
1649 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1650 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) …  in calculate_wm_set_for_vlevel()
1651 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1652 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1653 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1654 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1655 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1656 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;  in calculate_wm_set_for_vlevel()
1657 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;  in calculate_wm_set_for_vlevel()
1683 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn301_calculate_wm_and_dlg()
1688 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn301_calculate_wm_and_dlg()
1693 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn301_calculate_wm_and_dlg()
1699 						&context->bw_ctx.dml, pipes, pipe_cnt);  in dcn301_calculate_wm_and_dlg()
1705 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn…  in dcn301_calculate_wm_and_dlg()
1706 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,…  in dcn301_calculate_wm_and_dlg()
1709 			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;  in dcn301_calculate_wm_and_dlg()
1710 			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;  in dcn301_calculate_wm_and_dlg()
1889 	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);  in dcn301_resource_construct()