297 #define SRI(reg_name, block, id)\  argument
300 #define SRI2(reg_name, block, id)\  argument
303 #define SRII(reg_name, block, id)\  argument
307 #define DCCG_SRII(reg_name, block, id)\  argument
311 #define VUPDATE_SRII(reg_name, block, id)\  argument
315 #define SRII_DWB(reg_name, temp_name, block, id)\  argument
319 #define SRII_MPC_RMU(reg_name, block, id)\  argument
335 #define vmid_regs(id)\  argument
389 #define vpg_regs(id)\  argument
418 #define afmt_regs(id)\  argument
447 #define audio_regs(id)\  argument
478 #define stream_enc_regs(id)\  argument
543 		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)  in dcn303_clock_source_create()
584 #define hubp_regs(id)\  argument
615 #define dpp_regs(id)\  argument
646 #define opp_regs(id)\  argument
675 #define optc_regs(id)\  argument
740 #define dsc_regsDCN20(id)\  argument
769 #define dwbc_regs_dcn3(id)\  argument
804 #define mcif_wb_regs_dcn3(id)\  argument
839 #define aux_engine_regs(id)\  argument
873 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }  argument
912 #define link_regs(id, phyid)\  argument
934 #define aux_regs(id)\  argument
942 #define hpd_regs(id)\  argument
1410 #define abm_regs(id)\  argument