Lines Matching refs:dc
59 dc->ctx->logger
66 void dcn31_init_hw(struct dc *dc) in dcn31_init_hw() argument
68 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
69 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw()
70 struct dc_bios *dcb = dc->ctx->dc_bios; in dcn31_init_hw()
71 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw()
76 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn31_init_hw()
77 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn31_init_hw()
79 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_init_hw()
85 if (!dc->debug.disable_clock_gate) { in dcn31_init_hw()
102 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
103 hws->funcs.disable_vga(dc->hwseq); in dcn31_init_hw()
109 if (dc->debug.enable_mem_low_power.bits.dmcu) { in dcn31_init_hw()
111 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { in dcn31_init_hw()
117 if (dc->debug.enable_mem_low_power.bits.optc) { in dcn31_init_hw()
122 if (dc->debug.enable_mem_low_power.bits.vga) { in dcn31_init_hw()
127 if (dc->ctx->dc_bios->fw_info_valid) { in dcn31_init_hw()
129 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; in dcn31_init_hw()
131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_init_hw()
135 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, in dcn31_init_hw()
152 for (i = 0; i < dc->link_count; i++) { in dcn31_init_hw()
157 struct dc_link *link = dc->links[i]; in dcn31_init_hw()
173 if (dc->config.power_down_display_on_boot) { in dcn31_init_hw()
177 for (i = 0; i < dc->link_count; i++) { in dcn31_init_hw()
178 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) in dcn31_init_hw()
182 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in dcn31_init_hw()
186 if (dc->links[i]->link_enc->funcs->get_dig_frontend) { in dcn31_init_hw()
189 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( in dcn31_init_hw()
190 dc->links[i]->link_enc); in dcn31_init_hw()
194 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { in dcn31_init_hw()
195 if (fe == dc->res_pool->stream_enc[j]->id) { in dcn31_init_hw()
196 dc->res_pool->stream_enc[j]->funcs->dp_blank( in dcn31_init_hw()
197 dc->res_pool->stream_enc[j]); in dcn31_init_hw()
202 dp_receiver_power_ctrl(dc->links[i], false); in dcn31_init_hw()
208 hws->funcs.enable_power_gating_plane(dc->hwseq, true); in dcn31_init_hw()
216 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { in dcn31_init_hw()
217 hws->funcs.init_pipes(dc, dc->current_state); in dcn31_init_hw()
218 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) in dcn31_init_hw()
219 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn31_init_hw()
220 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); in dcn31_init_hw()
228 if (dc->config.power_down_display_on_boot) { in dcn31_init_hw()
233 get_edp_links(dc, edp_links, &edp_num); in dcn31_init_hw()
239 dc->hwss.edp_backlight_control && in dcn31_init_hw()
240 dc->hwss.power_down && in dcn31_init_hw()
241 dc->hwss.edp_power_control) { in dcn31_init_hw()
242 dc->hwss.edp_backlight_control(edp_link, false); in dcn31_init_hw()
243 dc->hwss.power_down(dc); in dcn31_init_hw()
244 dc->hwss.edp_power_control(edp_link, false); in dcn31_init_hw()
250 for (i = 0; i < dc->link_count; i++) { in dcn31_init_hw()
251 struct dc_link *link = dc->links[i]; in dcn31_init_hw()
255 dc->hwss.power_down) { in dcn31_init_hw()
256 dc->hwss.power_down(dc); in dcn31_init_hw()
270 for (i = 0; i < dc->link_count; i++) { in dcn31_init_hw()
271 struct dc_link *link = dc->links[i]; in dcn31_init_hw()
277 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_init_hw()
285 if (!dc->debug.disable_clock_gate) { in dcn31_init_hw()
294 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) in dcn31_init_hw()
295 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn31_init_hw()
297 if (dc->clk_mgr->funcs->notify_wm_ranges) in dcn31_init_hw()
298 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); in dcn31_init_hw()
300 if (dc->clk_mgr->funcs->set_hard_max_memclk) in dcn31_init_hw()
301 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); in dcn31_init_hw()
303 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) in dcn31_init_hw()
304 dc->res_pool->hubbub->funcs->force_pstate_change_control( in dcn31_init_hw()
305 dc->res_pool->hubbub, false, false); in dcn31_init_hw()
306 if (dc->res_pool->hubbub->funcs->init_crb) in dcn31_init_hw()
307 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn31_init_hw()
319 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn31_dsc_pg_control()
410 void dcn31_z10_save_init(struct dc *dc) in dcn31_z10_save_init() argument
418 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn31_z10_save_init()
419 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn31_z10_save_init()
420 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); in dcn31_z10_save_init()
423 void dcn31_z10_restore(struct dc *dc) in dcn31_z10_restore() argument
431 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) in dcn31_z10_restore()
438 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); in dcn31_z10_restore()
439 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); in dcn31_z10_restore()
440 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); in dcn31_z10_restore()
448 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn31_hubp_pg_control()
477 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn31_init_sys_ctx() argument
498 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn31_init_sys_ctx()
502 struct dc *dc, in dcn31_reset_back_end_for_pipe() argument
508 DC_LOGGER_INIT(dc->ctx->logger); in dcn31_reset_back_end_for_pipe()
515 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn31_reset_back_end_for_pipe()
531 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn31_reset_back_end_for_pipe()
542 dc->hwss.disable_audio_stream(pipe_ctx); in dcn31_reset_back_end_for_pipe()
550 if (dc->caps.dynamic_audio == true) { in dcn31_reset_back_end_for_pipe()
553 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, in dcn31_reset_back_end_for_pipe()
568 struct dc *dc, in dcn31_reset_hw_ctx_wrap() argument
572 struct dce_hwseq *hws = dc->hwseq; in dcn31_reset_hw_ctx_wrap()
575 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { in dcn31_reset_hw_ctx_wrap()
577 &dc->current_state->res_ctx.pipe_ctx[i]; in dcn31_reset_hw_ctx_wrap()
590 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); in dcn31_reset_hw_ctx_wrap()
592 hws->funcs.enable_stream_gating(dc, pipe_ctx); in dcn31_reset_hw_ctx_wrap()
599 bool dcn31_is_abm_supported(struct dc *dc, in dcn31_is_abm_supported() argument
604 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_is_abm_supported()