159 struct vi_mqd {  struct
160 	uint32_t header;
161 	uint32_t compute_dispatch_initiator;
162 	uint32_t compute_dim_x;
163 	uint32_t compute_dim_y;
164 	uint32_t compute_dim_z;
165 	uint32_t compute_start_x;
166 	uint32_t compute_start_y;
167 	uint32_t compute_start_z;
168 	uint32_t compute_num_thread_x;
169 	uint32_t compute_num_thread_y;
170 	uint32_t compute_num_thread_z;
171 	uint32_t compute_pipelinestat_enable;
172 	uint32_t compute_perfcount_enable;
173 	uint32_t compute_pgm_lo;
174 	uint32_t compute_pgm_hi;
175 	uint32_t compute_tba_lo;
176 	uint32_t compute_tba_hi;
177 	uint32_t compute_tma_lo;
178 	uint32_t compute_tma_hi;
179 	uint32_t compute_pgm_rsrc1;
180 	uint32_t compute_pgm_rsrc2;
181 	uint32_t compute_vmid;
182 	uint32_t compute_resource_limits;
183 	uint32_t compute_static_thread_mgmt_se0;
184 	uint32_t compute_static_thread_mgmt_se1;
185 	uint32_t compute_tmpring_size;
186 	uint32_t compute_static_thread_mgmt_se2;
187 	uint32_t compute_static_thread_mgmt_se3;
188 	uint32_t compute_restart_x;
189 	uint32_t compute_restart_y;
190 	uint32_t compute_restart_z;
191 	uint32_t compute_thread_trace_enable;
192 	uint32_t compute_misc_reserved;
193 	uint32_t compute_dispatch_id;
194 	uint32_t compute_threadgroup_id;
195 	uint32_t compute_relaunch;
196 	uint32_t compute_wave_restore_addr_lo;
197 	uint32_t compute_wave_restore_addr_hi;
198 	uint32_t compute_wave_restore_control;
199 	uint32_t reserved9;
200 	uint32_t reserved10;
201 	uint32_t reserved11;
202 	uint32_t reserved12;
203 	uint32_t reserved13;
204 	uint32_t reserved14;
205 	uint32_t reserved15;
206 	uint32_t reserved16;
207 	uint32_t reserved17;
208 	uint32_t reserved18;
209 	uint32_t reserved19;
210 	uint32_t reserved20;
211 	uint32_t reserved21;
212 	uint32_t reserved22;
213 	uint32_t reserved23;
214 	uint32_t reserved24;
215 	uint32_t reserved25;
216 	uint32_t reserved26;
217 	uint32_t reserved27;
218 	uint32_t reserved28;
219 	uint32_t reserved29;
220 	uint32_t reserved30;
221 	uint32_t reserved31;
222 	uint32_t reserved32;
223 	uint32_t reserved33;
224 	uint32_t reserved34;
225 	uint32_t compute_user_data_0;
226 	uint32_t compute_user_data_1;
227 	uint32_t compute_user_data_2;
228 	uint32_t compute_user_data_3;
229 	uint32_t compute_user_data_4;
230 	uint32_t compute_user_data_5;
231 	uint32_t compute_user_data_6;
232 	uint32_t compute_user_data_7;
233 	uint32_t compute_user_data_8;
234 	uint32_t compute_user_data_9;
235 	uint32_t compute_user_data_10;
236 	uint32_t compute_user_data_11;
237 	uint32_t compute_user_data_12;
238 	uint32_t compute_user_data_13;
239 	uint32_t compute_user_data_14;
240 	uint32_t compute_user_data_15;
241 	uint32_t cp_compute_csinvoc_count_lo;
242 	uint32_t cp_compute_csinvoc_count_hi;
243 	uint32_t reserved35;
244 	uint32_t reserved36;
245 	uint32_t reserved37;
246 	uint32_t cp_mqd_query_time_lo;
247 	uint32_t cp_mqd_query_time_hi;
248 	uint32_t cp_mqd_connect_start_time_lo;
249 	uint32_t cp_mqd_connect_start_time_hi;
250 	uint32_t cp_mqd_connect_end_time_lo;
251 	uint32_t cp_mqd_connect_end_time_hi;
252 	uint32_t cp_mqd_connect_end_wf_count;
253 	uint32_t cp_mqd_connect_end_pq_rptr;
254 	uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
255 	uint32_t cp_mqd_connect_end_ib_rptr;
256 	uint32_t reserved38;
257 	uint32_t reserved39;
258 	uint32_t cp_mqd_save_start_time_lo;
259 	uint32_t cp_mqd_save_start_time_hi;
260 	uint32_t cp_mqd_save_end_time_lo;
261 	uint32_t cp_mqd_save_end_time_hi;
262 	uint32_t cp_mqd_restore_start_time_lo;
263 	uint32_t cp_mqd_restore_start_time_hi;
264 	uint32_t cp_mqd_restore_end_time_lo;
265 	uint32_t cp_mqd_restore_end_time_hi;
266 	uint32_t disable_queue;
267 	uint32_t reserved41;
268 	uint32_t gds_cs_ctxsw_cnt0;
269 	uint32_t gds_cs_ctxsw_cnt1;
270 	uint32_t gds_cs_ctxsw_cnt2;
271 	uint32_t gds_cs_ctxsw_cnt3;
272 	uint32_t reserved42;
273 	uint32_t reserved43;
274 	uint32_t cp_pq_exe_status_lo;
275 	uint32_t cp_pq_exe_status_hi;
276 	uint32_t cp_packet_id_lo;
277 	uint32_t cp_packet_id_hi;
278 	uint32_t cp_packet_exe_status_lo;
279 	uint32_t cp_packet_exe_status_hi;
280 	uint32_t gds_save_base_addr_lo;
281 	uint32_t gds_save_base_addr_hi;
282 	uint32_t gds_save_mask_lo;
283 	uint32_t gds_save_mask_hi;
284 	uint32_t ctx_save_base_addr_lo;
285 	uint32_t ctx_save_base_addr_hi;
286 	uint32_t dynamic_cu_mask_addr_lo;
287 	uint32_t dynamic_cu_mask_addr_hi;
288 	uint32_t cp_mqd_base_addr_lo;
289 	uint32_t cp_mqd_base_addr_hi;
290 	uint32_t cp_hqd_active;
291 	uint32_t cp_hqd_vmid;
292 	uint32_t cp_hqd_persistent_state;
293 	uint32_t cp_hqd_pipe_priority;
294 	uint32_t cp_hqd_queue_priority;
295 	uint32_t cp_hqd_quantum;
296 	uint32_t cp_hqd_pq_base_lo;
297 	uint32_t cp_hqd_pq_base_hi;
298 	uint32_t cp_hqd_pq_rptr;
299 	uint32_t cp_hqd_pq_rptr_report_addr_lo;
300 	uint32_t cp_hqd_pq_rptr_report_addr_hi;
301 	uint32_t cp_hqd_pq_wptr_poll_addr_lo;
302 	uint32_t cp_hqd_pq_wptr_poll_addr_hi;
303 	uint32_t cp_hqd_pq_doorbell_control;
304 	uint32_t cp_hqd_pq_wptr;
305 	uint32_t cp_hqd_pq_control;
306 	uint32_t cp_hqd_ib_base_addr_lo;
307 	uint32_t cp_hqd_ib_base_addr_hi;
308 	uint32_t cp_hqd_ib_rptr;
309 	uint32_t cp_hqd_ib_control;
310 	uint32_t cp_hqd_iq_timer;
311 	uint32_t cp_hqd_iq_rptr;
312 	uint32_t cp_hqd_dequeue_request;
313 	uint32_t cp_hqd_dma_offload;
314 	uint32_t cp_hqd_sema_cmd;
315 	uint32_t cp_hqd_msg_type;
316 	uint32_t cp_hqd_atomic0_preop_lo;
317 	uint32_t cp_hqd_atomic0_preop_hi;
318 	uint32_t cp_hqd_atomic1_preop_lo;
319 	uint32_t cp_hqd_atomic1_preop_hi;
320 	uint32_t cp_hqd_hq_status0;
321 	uint32_t cp_hqd_hq_control0;
322 	uint32_t cp_mqd_control;
323 	uint32_t cp_hqd_hq_status1;
324 	uint32_t cp_hqd_hq_control1;
325 	uint32_t cp_hqd_eop_base_addr_lo;
326 	uint32_t cp_hqd_eop_base_addr_hi;
327 	uint32_t cp_hqd_eop_control;
328 	uint32_t cp_hqd_eop_rptr;
329 	uint32_t cp_hqd_eop_wptr;
330 	uint32_t cp_hqd_eop_done_events;
331 	uint32_t cp_hqd_ctx_save_base_addr_lo;
332 	uint32_t cp_hqd_ctx_save_base_addr_hi;
333 	uint32_t cp_hqd_ctx_save_control;
334 	uint32_t cp_hqd_cntl_stack_offset;
335 	uint32_t cp_hqd_cntl_stack_size;
336 	uint32_t cp_hqd_wg_state_offset;
337 	uint32_t cp_hqd_ctx_save_size;
338 	uint32_t cp_hqd_gds_resource_state;
339 	uint32_t cp_hqd_error;
340 	uint32_t cp_hqd_eop_wptr_mem;
341 	uint32_t cp_hqd_eop_dones;
342 	uint32_t reserved46;
343 	uint32_t reserved47;
344 	uint32_t reserved48;
345 	uint32_t reserved49;
346 	uint32_t reserved50;
347 	uint32_t reserved51;
348 	uint32_t reserved52;
349 	uint32_t reserved53;
350 	uint32_t reserved54;
351 	uint32_t reserved55;
352 	uint32_t iqtimer_pkt_header;
353 	uint32_t iqtimer_pkt_dw0;
354 	uint32_t iqtimer_pkt_dw1;
355 	uint32_t iqtimer_pkt_dw2;
356 	uint32_t iqtimer_pkt_dw3;
357 	uint32_t iqtimer_pkt_dw4;
358 	uint32_t iqtimer_pkt_dw5;
359 	uint32_t iqtimer_pkt_dw6;
360 	uint32_t iqtimer_pkt_dw7;
361 	uint32_t iqtimer_pkt_dw8;
362 	uint32_t iqtimer_pkt_dw9;
363 	uint32_t iqtimer_pkt_dw10;
364 	uint32_t iqtimer_pkt_dw11;
365 	uint32_t iqtimer_pkt_dw12;
366 	uint32_t iqtimer_pkt_dw13;
367 	uint32_t iqtimer_pkt_dw14;
368 	uint32_t iqtimer_pkt_dw15;
369 	uint32_t iqtimer_pkt_dw16;
370 	uint32_t iqtimer_pkt_dw17;
371 	uint32_t iqtimer_pkt_dw18;
372 	uint32_t iqtimer_pkt_dw19;
373 	uint32_t iqtimer_pkt_dw20;
374 	uint32_t iqtimer_pkt_dw21;
375 	uint32_t iqtimer_pkt_dw22;
376 	uint32_t iqtimer_pkt_dw23;
377 	uint32_t iqtimer_pkt_dw24;
378 	uint32_t iqtimer_pkt_dw25;
379 	uint32_t iqtimer_pkt_dw26;
380 	uint32_t iqtimer_pkt_dw27;
381 	uint32_t iqtimer_pkt_dw28;
382 	uint32_t iqtimer_pkt_dw29;
383 	uint32_t iqtimer_pkt_dw30;
384 	uint32_t iqtimer_pkt_dw31;
385 	uint32_t reserved56;
386 	uint32_t reserved57;
387 	uint32_t reserved58;
388 	uint32_t set_resources_header;
389 	uint32_t set_resources_dw1;
390 	uint32_t set_resources_dw2;
391 	uint32_t set_resources_dw3;
392 	uint32_t set_resources_dw4;
393 	uint32_t set_resources_dw5;
394 	uint32_t set_resources_dw6;
395 	uint32_t set_resources_dw7;
419 struct vi_mqd_allocation {  argument
420 	struct vi_mqd mqd;  argument