Lines Matching refs:entries
302 voltage_table->entries[i].value = in phm_get_svi2_voltage_table_v0()
303 voltage_dependency_table->entries[i].v; in phm_get_svi2_voltage_table_v0()
304 voltage_table->entries[i].smio_low = 0; in phm_get_svi2_voltage_table_v0()
676 pcie_table->entries[i].gen_speed), in smu7_setup_default_pcie_table()
678 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
809 allowed_vdd_sclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v0()
811 allowed_vdd_sclk_table->entries[i].clk; in smu7_setup_dpm_tables_v0()
823 allowed_vdd_mclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v0()
825 allowed_vdd_mclk_table->entries[i].clk; in smu7_setup_dpm_tables_v0()
833 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
834 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; in smu7_setup_dpm_tables_v0()
845 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
859 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
902 dep_sclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v1()
905 dep_sclk_table->entries[i].clk; in smu7_setup_dpm_tables_v1()
913 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()
919 dep_mclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v1()
921 dep_mclk_table->entries[i].clk; in smu7_setup_dpm_tables_v1()
929 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()
943 struct phm_odn_performance_level *entries; in smu7_odn_initial_default_setting() local
953 entries = odn_table->odn_core_clock_dpm_levels.entries; in smu7_odn_initial_default_setting()
955 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; in smu7_odn_initial_default_setting()
956 entries[i].enabled = true; in smu7_odn_initial_default_setting()
957 entries[i].vddc = dep_sclk_table->entries[i].vddc; in smu7_odn_initial_default_setting()
965 entries = odn_table->odn_memory_clock_dpm_levels.entries; in smu7_odn_initial_default_setting()
967 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; in smu7_odn_initial_default_setting()
968 entries[i].enabled = true; in smu7_odn_initial_default_setting()
969 entries[i].vddc = dep_mclk_table->entries[i].vddc; in smu7_odn_initial_default_setting()
995 || min_vddc > dep_sclk_table->entries[0].vddc) in smu7_setup_voltage_range_from_vbios()
996 min_vddc = dep_sclk_table->entries[0].vddc; in smu7_setup_voltage_range_from_vbios()
999 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) in smu7_setup_voltage_range_from_vbios()
1000 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; in smu7_setup_voltage_range_from_vbios()
1021 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != in smu7_check_dpm_table_updated()
1029 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != in smu7_check_dpm_table_updated()
1040 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { in smu7_check_dpm_table_updated()
1049 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { in smu7_check_dpm_table_updated()
2024 if (sclk_table->entries[j].clk == sclk && in smu7_get_evv_voltages()
2025 sclk_table->entries[j].cks_enable == 0) { in smu7_get_evv_voltages()
2058 if (sclk_table->entries[j].clk == sclk && in smu7_get_evv_voltages()
2059 sclk_table->entries[j].cks_enable == 0) { in smu7_get_evv_voltages()
2131 &lookup_table->entries[i].us_vdd, leakage_table); in smu7_patch_lookup_table_with_leakage()
2166 voltage_id = sclk_table->entries[entry_id].vddInd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2167 sclk_table->entries[entry_id].vddgfx = in smu7_patch_voltage_dependency_tables_with_lookup_table()
2168 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2172 voltage_id = sclk_table->entries[entry_id].vddInd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2173 sclk_table->entries[entry_id].vddc = in smu7_patch_voltage_dependency_tables_with_lookup_table()
2174 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2179 voltage_id = mclk_table->entries[entry_id].vddInd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2180 mclk_table->entries[entry_id].vddc = in smu7_patch_voltage_dependency_tables_with_lookup_table()
2181 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2185 voltage_id = mm_table->entries[entry_id].vddcInd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2186 mm_table->entries[entry_id].vddc = in smu7_patch_voltage_dependency_tables_with_lookup_table()
2187 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; in smu7_patch_voltage_dependency_tables_with_lookup_table()
2211 if (look_up_table->entries[i].us_vdd == record->us_vdd) { in phm_add_voltage()
2212 if (look_up_table->entries[i].us_calculated == 1) in phm_add_voltage()
2218 look_up_table->entries[i].us_calculated = 1; in phm_add_voltage()
2219 look_up_table->entries[i].us_vdd = record->us_vdd; in phm_add_voltage()
2220 look_up_table->entries[i].us_cac_low = record->us_cac_low; in phm_add_voltage()
2221 look_up_table->entries[i].us_cac_mid = record->us_cac_mid; in phm_add_voltage()
2222 look_up_table->entries[i].us_cac_high = record->us_cac_high; in phm_add_voltage()
2243 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) in smu7_calc_voltage_dependency_tables()
2244 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + in smu7_calc_voltage_dependency_tables()
2245 sclk_table->entries[entry_id].vdd_offset - 0xFFFF; in smu7_calc_voltage_dependency_tables()
2247 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + in smu7_calc_voltage_dependency_tables()
2248 sclk_table->entries[entry_id].vdd_offset; in smu7_calc_voltage_dependency_tables()
2250 sclk_table->entries[entry_id].vddc = in smu7_calc_voltage_dependency_tables()
2258 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) in smu7_calc_voltage_dependency_tables()
2259 v_record.us_vdd = mclk_table->entries[entry_id].vddc + in smu7_calc_voltage_dependency_tables()
2260 mclk_table->entries[entry_id].vdd_offset - 0xFFFF; in smu7_calc_voltage_dependency_tables()
2262 v_record.us_vdd = mclk_table->entries[entry_id].vddc + in smu7_calc_voltage_dependency_tables()
2263 mclk_table->entries[entry_id].vdd_offset; in smu7_calc_voltage_dependency_tables()
2265 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = in smu7_calc_voltage_dependency_tables()
2283 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) in smu7_calc_mm_voltage_dependency_table()
2284 v_record.us_vdd = mm_table->entries[entry_id].vddc + in smu7_calc_mm_voltage_dependency_table()
2285 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; in smu7_calc_mm_voltage_dependency_table()
2287 v_record.us_vdd = mm_table->entries[entry_id].vddc + in smu7_calc_mm_voltage_dependency_table()
2288 mm_table->entries[entry_id].vddgfx_offset; in smu7_calc_mm_voltage_dependency_table()
2291 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = in smu7_calc_mm_voltage_dependency_table()
2311 if (lookup_table->entries[j].us_vdd < in smu7_sort_lookup_table()
2312 lookup_table->entries[j - 1].us_vdd) { in smu7_sort_lookup_table()
2313 swap(lookup_table->entries[j - 1], in smu7_sort_lookup_table()
2314 lookup_table->entries[j]); in smu7_sort_lookup_table()
2385 highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; in smu7_find_highest_vddc()
2388 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 && in smu7_find_highest_vddc()
2389 lookup_table->entries[i].us_vdd > highest_voltage) in smu7_find_highest_vddc()
2390 highest_voltage = lookup_table->entries[i].us_vdd; in smu7_find_highest_vddc()
2421 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v1()
2423 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v1()
2429 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; in smu7_set_private_data_based_on_pptable_v1()
2431 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; in smu7_set_private_data_based_on_pptable_v1()
2472 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) in smu7_patch_voltage_workaround()
2476 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { in smu7_patch_voltage_workaround()
2477 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; in smu7_patch_voltage_workaround()
2607 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vddc()
2621 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vddci()
2635 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_vce_vddc()
2650 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_uvd_vddc()
2664 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, in smu7_patch_vddc_shed_limit()
2678 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_samu_vddc()
2692 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, in smu7_patch_acp_vddc()
2726 vddc = (uint32_t)(tab->entries[i].Vddc); in smu7_patch_cac_vddc()
2728 tab->entries[i].Vddc = (uint16_t)vddc; in smu7_patch_cac_vddc()
2813 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; in smu7_set_private_data_based_on_pptable_v0()
2814 …data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->co… in smu7_set_private_data_based_on_pptable_v0()
2817 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v0()
2819 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v0()
2821 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; in smu7_set_private_data_based_on_pptable_v0()
2824 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; in smu7_set_private_data_based_on_pptable_v0()
2825 …data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table-… in smu7_set_private_data_based_on_pptable_v0()
2829 …x_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.… in smu7_set_private_data_based_on_pptable_v0()
3149 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { in smu7_get_profiling_clk()
3150 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; in smu7_get_profiling_clk()
3157 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; in smu7_get_profiling_clk()
3167 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { in smu7_get_profiling_clk()
3168 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk; in smu7_get_profiling_clk()
3175 tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; in smu7_get_profiling_clk()
3331 table_info->vdd_dep_on_sclk->entries[count].clk) { in smu7_apply_state_adjust_rules()
3333 table_info->vdd_dep_on_sclk->entries[count].clk; in smu7_apply_state_adjust_rules()
3339 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; in smu7_apply_state_adjust_rules()
3403 if (data->mclk_latency_table.entries[i].latency <= latency) { in smu7_apply_state_adjust_rules()
3406 if ((data->mclk_latency_table.entries[i].frequency >= in smu7_apply_state_adjust_rules()
3408 (data->mclk_latency_table.entries[i].frequency <= in smu7_apply_state_adjust_rules()
3410 mclk = data->mclk_latency_table.entries[i].frequency; in smu7_apply_state_adjust_rules()
3620 performance_level->memory_clock = mclk_dep_table->entries in smu7_get_pp_table_entry_callback_func_v1()
3623 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries in smu7_get_pp_table_entry_callback_func_v1()
3626 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries in smu7_get_pp_table_entry_callback_func_v1()
3635 performance_level->memory_clock = mclk_dep_table->entries in smu7_get_pp_table_entry_callback_func_v1()
3639 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries in smu7_get_pp_table_entry_callback_func_v1()
3642 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries in smu7_get_pp_table_entry_callback_func_v1()
3676 if (dep_mclk_table->entries[0].clk != in smu7_get_pp_table_entry_v1()
3680 if (dep_mclk_table->entries[0].vddci != in smu7_get_pp_table_entry_v1()
3824 if (dep_mclk_table->entries[0].clk != in smu7_get_pp_table_entry_v0()
3828 if (dep_mclk_table->entries[0].v != in smu7_get_pp_table_entry_v0()
4208 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4209 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4215 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4216 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4973 i, odn_sclk_table->entries[i].clock/100, in smu7_print_clock_levels()
4974 odn_sclk_table->entries[i].vddc); in smu7_print_clock_levels()
4982 i, odn_mclk_table->entries[i].clock/100, in smu7_print_clock_levels()
4983 odn_mclk_table->entries[i].vddc); in smu7_print_clock_levels()
5129 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; in smu7_get_sclks()
5134 clocks->clock[i] = sclk_table->entries[i].clk * 10; in smu7_get_sclks()
5166 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; in smu7_get_mclks()
5168 dep_mclk_table->entries[i].clk); in smu7_get_mclks()
5174 clocks->clock[i] = mclk_table->entries[i].clk * 10; in smu7_get_mclks()
5208 if (dep_sclk_table->entries[i].clk) { in smu7_get_sclks_with_latency()
5210 dep_sclk_table->entries[i].clk * 10; in smu7_get_sclks_with_latency()
5231 if (dep_mclk_table->entries[i].clk) { in smu7_get_mclks_with_latency()
5233 dep_mclk_table->entries[i].clk * 10; in smu7_get_mclks_with_latency()
5234 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = in smu7_get_mclks_with_latency()
5235 dep_mclk_table->entries[i].clk; in smu7_get_mclks_with_latency()
5237 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = in smu7_get_mclks_with_latency()
5238 smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); in smu7_get_mclks_with_latency()
5294 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5295 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5296 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5297 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { in smu7_set_watermarks_for_clocks_ranges()
5486 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
5487 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
5488 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; in smu7_odn_edit_dpm_table()
5489 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; in smu7_odn_edit_dpm_table()
5490 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol; in smu7_odn_edit_dpm_table()