Lines Matching refs:performance_levels
2402 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2403 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2421 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2422 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2428 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2437 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2496 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
3163 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3164 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3181 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3182 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3470 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3471 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3475 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3476 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3477 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3478 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3479 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3480 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3481 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
3482 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3496 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
3497 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
3500 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3501 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3504 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3505 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3508 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3509 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3512 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3513 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3520 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3521 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3523 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3524 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3528 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3529 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3531 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3532 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3543 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3544 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3545 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3546 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3549 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3551 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3552 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3555 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3556 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3560 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3561 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3562 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3563 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3568 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3570 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3571 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3574 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3575 ps->performance_levels[i].vddci = vddci; in si_apply_state_adjust_rules()
3579 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3580 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3581 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()
3582 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()
3588 &ps->performance_levels[i]); in si_apply_state_adjust_rules()
3591 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3592 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3594 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
3595 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3597 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3598 max_limits->vddci, &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3600 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3601 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3604 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3610 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3611 &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3616 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
4772 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4840 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4856 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4864 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4882 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4888 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4889 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4890 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4903 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4905 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
5555 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5556 state->performance_levels[i].sclk, in si_populate_smc_t()
5598 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5647 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5671 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5681 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
6079 &state->performance_levels[i], in si_convert_mc_reg_table_to_smc()
6098 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
6158 pcie_speed = state->performance_levels[i].pcie_gen; in si_get_maximum_link_speed()
7138 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info()
7491 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7871 return requested_state->performance_levels[0].sclk; in si_dpm_get_sclk()
7873 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in si_dpm_get_sclk()
7883 return requested_state->performance_levels[0].mclk; in si_dpm_get_mclk()
7885 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in si_dpm_get_mclk()
7901 pl = &ps->performance_levels[i]; in si_dpm_print_power_state()
7963 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), in si_check_state_equal()
7964 &(si_rps->performance_levels[i]))) { in si_check_state_equal()
7996 sclk = ps->performance_levels[pl_index].sclk; in si_dpm_read_sensor()
8004 mclk = ps->performance_levels[pl_index].mclk; in si_dpm_read_sensor()