Lines Matching refs:sclk
1831 SISLANDS_SMC_SCLK_VALUE *sclk);
2402 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2403 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2421 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2422 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2496 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2934 u32 sclk = 0; in si_init_smc_spll_table() local
2947 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); in si_init_smc_spll_table()
2979 sclk += 512; in si_init_smc_spll_table()
3163 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3164 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3181 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3182 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3272 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
3275 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
3278 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
3279 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3280 pl->sclk = btc_get_valid_sclk(adev, in btc_adjust_clock_combinations()
3281 max_limits->sclk, in btc_adjust_clock_combinations()
3286 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3289 pl->sclk - in btc_adjust_clock_combinations()
3414 u32 mclk, sclk; in si_apply_state_adjust_rules() local
3477 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3478 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3496 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
3497 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
3512 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3513 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3528 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3531 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3536 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3537 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3543 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3549 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3551 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3552 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3555 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3560 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3561 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3594 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
4652 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4659 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
4745 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); in si_populate_memory_timing_parameters()
4748 pl->sclk, in si_populate_memory_timing_parameters()
4842 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4844 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4846 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_initial_state()
4848 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_initial_state()
4850 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = in si_populate_smc_initial_state()
4852 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in si_populate_smc_initial_state()
4855 table->initialState.level.sclk.sclk_value = in si_populate_smc_initial_state()
4856 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4889 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
5040 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
5042 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
5044 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_acpi_state()
5046 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_acpi_state()
5050 table->ACPIState.level.sclk.sclk_value = 0; in si_populate_smc_acpi_state()
5227 SISLANDS_SMC_SCLK_VALUE *sclk) in si_calculate_sclk_params() argument
5284 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
5285 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; in si_calculate_sclk_params()
5286 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; in si_calculate_sclk_params()
5287 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; in si_calculate_sclk_params()
5288 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; in si_calculate_sclk_params()
5289 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; in si_calculate_sclk_params()
5290 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
5297 SISLANDS_SMC_SCLK_VALUE *sclk) in si_populate_sclk_value() argument
5304 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); in si_populate_sclk_value()
5305 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); in si_populate_sclk_value()
5306 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); in si_populate_sclk_value()
5307 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); in si_populate_sclk_value()
5308 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); in si_populate_sclk_value()
5309 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); in si_populate_sclk_value()
5310 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); in si_populate_sclk_value()
5438 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
5481 pl->sclk, in si_convert_power_level_to_smc()
5515 pl->sclk, in si_convert_power_level_to_smc()
5555 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5556 state->performance_levels[i].sclk, in si_populate_smc_t()
5647 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5681 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
7143 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_pplib_clock_info()
7144 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_pplib_clock_info()
7190 pl->sclk = adev->clock.default_sclk; in si_parse_pplib_clock_info()
7198 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
7285 u32 sclk, mclk; in si_parse_power_table() local
7289 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_power_table()
7290 sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_power_table()
7293 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7453 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7494 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7871 return requested_state->performance_levels[0].sclk; in si_dpm_get_sclk()
7873 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in si_dpm_get_sclk()
7904 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_print_power_state()
7907 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in si_dpm_print_power_state()
7927 (si_cpl1->sclk == si_cpl2->sclk) && in si_are_power_levels_equal()
7984 uint32_t sclk, mclk; in si_dpm_read_sensor() local
7996 sclk = ps->performance_levels[pl_index].sclk; in si_dpm_read_sensor()
7997 *((uint32_t *)value) = sclk; in si_dpm_read_sensor()