Lines Matching refs:GraphicsLevel

695 				offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);  in tonga_populate_all_graphic_levels()
700 	SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;  in tonga_populate_all_graphic_levels()
713 					&(smu_data->smc_state_table.GraphicsLevel[i]));  in tonga_populate_all_graphic_levels()
719 			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;  in tonga_populate_all_graphic_levels()
723 	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;  in tonga_populate_all_graphic_levels()
727 		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =  in tonga_populate_all_graphic_levels()
741 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =  in tonga_populate_all_graphic_levels()
771 			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;  in tonga_populate_all_graphic_levels()
774 		smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;  in tonga_populate_all_graphic_levels()
777 		smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;  in tonga_populate_all_graphic_levels()
1192 			smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;  in tonga_populate_smc_acpi_level()
1674 			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].  in tonga_populate_clock_stretcher_data_table()
1718 					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);  in tonga_populate_clock_stretcher_data_table()
3155 			smu_data->smc_state_table.GraphicsLevel;  in tonga_update_dpm_settings()
3157 			offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);  in tonga_update_dpm_settings()