161 #define ICN6211_DSI(icn, seq...)				\  macro
173 	ICN6211_DSI(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);  in chipone_enable()
175 	ICN6211_DSI(icn, HACTIVE_LI, mode->hdisplay & 0xff);  in chipone_enable()
177 	ICN6211_DSI(icn, VACTIVE_LI, mode->vdisplay & 0xff);  in chipone_enable()
183 	ICN6211_DSI(icn, VACTIVE_HACTIVE_HI,  in chipone_enable()
191 	ICN6211_DSI(icn, HFP_LI, hfp & 0xff);  in chipone_enable()
192 	ICN6211_DSI(icn, HSYNC_LI, hsync & 0xff);  in chipone_enable()
193 	ICN6211_DSI(icn, HBP_LI, hbp & 0xff);  in chipone_enable()
195 	ICN6211_DSI(icn, HFP_HSW_HBP_HI,  in chipone_enable()
200 	ICN6211_DSI(icn, VFP, mode->vsync_start - mode->vdisplay);  in chipone_enable()
202 	ICN6211_DSI(icn, VSYNC, mode->vsync_end - mode->vsync_start);  in chipone_enable()
204 	ICN6211_DSI(icn, VBP, mode->vtotal - mode->vsync_end);  in chipone_enable()
207 	ICN6211_DSI(icn, SYNC_EVENT_DLY, 0x80);  in chipone_enable()
208 	ICN6211_DSI(icn, HFP_MIN, hfp & 0xff);  in chipone_enable()
209 	ICN6211_DSI(icn, MIPI_PD_CK_LANE, 0xa0);  in chipone_enable()
210 	ICN6211_DSI(icn, PLL_CTRL(12), 0xff);  in chipone_enable()
211 	ICN6211_DSI(icn, BIST_POL, BIST_POL_DE_POL);  in chipone_enable()
212 	ICN6211_DSI(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK);  in chipone_enable()
213 	ICN6211_DSI(icn, PLL_REF_DIV, 0x71);  in chipone_enable()
214 	ICN6211_DSI(icn, PLL_INT(0), 0x2b);  in chipone_enable()
215 	ICN6211_DSI(icn, SYS_CTRL(0), 0x40);  in chipone_enable()
216 	ICN6211_DSI(icn, SYS_CTRL(1), 0x98);  in chipone_enable()
219 	ICN6211_DSI(icn, MIPI_FORCE_0, 0x20);  in chipone_enable()
220 	ICN6211_DSI(icn, PLL_CTRL(1), 0x20);  in chipone_enable()
221 	ICN6211_DSI(icn, CONFIG_FINISH, 0x10);  in chipone_enable()