Lines Matching refs:ctx
237 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, in fimd_set_bits() argument
240 val = (val & mask) | (readl(ctx->regs + reg) & ~mask); in fimd_set_bits()
241 writel(val, ctx->regs + reg); in fimd_set_bits()
246 struct fimd_context *ctx = crtc->ctx; in fimd_enable_vblank() local
249 if (ctx->suspended) in fimd_enable_vblank()
252 if (!test_and_set_bit(0, &ctx->irq_flags)) { in fimd_enable_vblank()
253 val = readl(ctx->regs + VIDINTCON0); in fimd_enable_vblank()
257 if (ctx->i80_if) { in fimd_enable_vblank()
270 writel(val, ctx->regs + VIDINTCON0); in fimd_enable_vblank()
278 struct fimd_context *ctx = crtc->ctx; in fimd_disable_vblank() local
281 if (ctx->suspended) in fimd_disable_vblank()
284 if (test_and_clear_bit(0, &ctx->irq_flags)) { in fimd_disable_vblank()
285 val = readl(ctx->regs + VIDINTCON0); in fimd_disable_vblank()
289 if (ctx->i80_if) { in fimd_disable_vblank()
296 writel(val, ctx->regs + VIDINTCON0); in fimd_disable_vblank()
302 struct fimd_context *ctx = crtc->ctx; in fimd_wait_for_vblank() local
304 if (ctx->suspended) in fimd_wait_for_vblank()
307 atomic_set(&ctx->wait_vsync_event, 1); in fimd_wait_for_vblank()
313 if (!wait_event_timeout(ctx->wait_vsync_queue, in fimd_wait_for_vblank()
314 !atomic_read(&ctx->wait_vsync_event), in fimd_wait_for_vblank()
316 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in fimd_wait_for_vblank()
319 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, in fimd_enable_video_output() argument
322 u32 val = readl(ctx->regs + WINCON(win)); in fimd_enable_video_output()
329 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
332 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, in fimd_enable_shadow_channel_path() argument
336 u32 val = readl(ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
343 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
348 struct fimd_context *ctx = crtc->ctx; in fimd_clear_channels() local
353 ret = pm_runtime_resume_and_get(ctx->dev); in fimd_clear_channels()
355 dev_err(ctx->dev, "failed to enable FIMD device.\n"); in fimd_clear_channels()
359 clk_prepare_enable(ctx->bus_clk); in fimd_clear_channels()
360 clk_prepare_enable(ctx->lcd_clk); in fimd_clear_channels()
364 u32 val = readl(ctx->regs + WINCON(win)); in fimd_clear_channels()
367 fimd_enable_video_output(ctx, win, false); in fimd_clear_channels()
369 if (ctx->driver_data->has_shadowcon) in fimd_clear_channels()
370 fimd_enable_shadow_channel_path(ctx, win, in fimd_clear_channels()
379 ctx->suspended = false; in fimd_clear_channels()
381 fimd_enable_vblank(ctx->crtc); in fimd_clear_channels()
382 fimd_wait_for_vblank(ctx->crtc); in fimd_clear_channels()
383 fimd_disable_vblank(ctx->crtc); in fimd_clear_channels()
385 ctx->suspended = true; in fimd_clear_channels()
388 clk_disable_unprepare(ctx->lcd_clk); in fimd_clear_channels()
389 clk_disable_unprepare(ctx->bus_clk); in fimd_clear_channels()
391 pm_runtime_put(ctx->dev); in fimd_clear_channels()
401 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_check() local
406 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); in fimd_atomic_check()
412 if (ctx->i80_if) { in fimd_atomic_check()
420 lcd_rate = clk_get_rate(ctx->lcd_clk); in fimd_atomic_check()
422 DRM_DEV_ERROR(ctx->dev, in fimd_atomic_check()
431 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", in fimd_atomic_check()
436 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; in fimd_atomic_check()
441 static void fimd_setup_trigger(struct fimd_context *ctx) in fimd_setup_trigger() argument
443 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; in fimd_setup_trigger()
444 u32 trg_type = ctx->driver_data->trg_type; in fimd_setup_trigger()
450 if (ctx->driver_data->has_hw_trigger) in fimd_setup_trigger()
452 if (ctx->driver_data->has_trigger_per_te) in fimd_setup_trigger()
463 struct fimd_context *ctx = crtc->ctx; in fimd_commit() local
465 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_commit()
466 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_commit()
469 if (ctx->suspended) in fimd_commit()
476 if (ctx->i80_if) { in fimd_commit()
477 val = ctx->i80ifcon | I80IFEN_ENABLE; in fimd_commit()
484 if (driver_data->has_vtsel && ctx->sysreg && in fimd_commit()
485 regmap_update_bits(ctx->sysreg, in fimd_commit()
489 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
498 vidcon1 = ctx->vidcon1; in fimd_commit()
503 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
513 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
523 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
527 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
530 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, in fimd_commit()
534 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
542 if (driver_data->has_mic_bypass && ctx->sysreg && in fimd_commit()
543 regmap_update_bits(ctx->sysreg, in fimd_commit()
547 DRM_DEV_ERROR(ctx->dev, in fimd_commit()
557 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
559 fimd_setup_trigger(ctx); in fimd_commit()
565 val = ctx->vidcon0; in fimd_commit()
568 if (ctx->driver_data->has_clksel) in fimd_commit()
571 if (ctx->clkdiv > 1) in fimd_commit()
572 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
574 writel(val, ctx->regs + VIDCON0); in fimd_commit()
577 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, in fimd_win_set_bldeq() argument
600 fimd_set_bits(ctx, BLENDEQx(win), mask, val); in fimd_win_set_bldeq()
603 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, in fimd_win_set_bldmod() argument
621 fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); in fimd_win_set_bldmod()
630 writel(val, ctx->regs + VIDOSD_C(win)); in fimd_win_set_bldmod()
634 writel(val, ctx->regs + VIDWnALPHA0(win)); in fimd_win_set_bldmod()
638 writel(val, ctx->regs + VIDWnALPHA1(win)); in fimd_win_set_bldmod()
640 fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, in fimd_win_set_bldmod()
644 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, in fimd_win_set_pixfmt() argument
647 struct exynos_drm_plane *plane = &ctx->planes[win]; in fimd_win_set_pixfmt()
664 if (ctx->driver_data->has_limited_fmt && !win) { in fimd_win_set_pixfmt()
710 fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); in fimd_win_set_pixfmt()
714 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); in fimd_win_set_pixfmt()
715 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); in fimd_win_set_pixfmt()
719 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) in fimd_win_set_colkey() argument
728 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); in fimd_win_set_colkey()
729 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); in fimd_win_set_colkey()
739 static void fimd_shadow_protect_win(struct fimd_context *ctx, in fimd_shadow_protect_win() argument
754 if (ctx->driver_data->has_shadowcon) { in fimd_shadow_protect_win()
762 val = readl(ctx->regs + reg); in fimd_shadow_protect_win()
767 writel(val, ctx->regs + reg); in fimd_shadow_protect_win()
772 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_begin() local
775 if (ctx->suspended) in fimd_atomic_begin()
779 fimd_shadow_protect_win(ctx, i, true); in fimd_atomic_begin()
784 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_flush() local
787 if (ctx->suspended) in fimd_atomic_flush()
791 fimd_shadow_protect_win(ctx, i, false); in fimd_atomic_flush()
801 struct fimd_context *ctx = crtc->ctx; in fimd_update_plane() local
810 if (ctx->suspended) in fimd_update_plane()
819 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); in fimd_update_plane()
824 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); in fimd_update_plane()
826 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
829 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", in fimd_update_plane()
839 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); in fimd_update_plane()
846 writel(val, ctx->regs + VIDOSD_A(win)); in fimd_update_plane()
858 writel(val, ctx->regs + VIDOSD_B(win)); in fimd_update_plane()
860 DRM_DEV_DEBUG_KMS(ctx->dev, in fimd_update_plane()
870 writel(val, ctx->regs + offset); in fimd_update_plane()
872 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", in fimd_update_plane()
876 fimd_win_set_pixfmt(ctx, win, fb, state->src.w); in fimd_update_plane()
880 fimd_win_set_colkey(ctx, win); in fimd_update_plane()
882 fimd_enable_video_output(ctx, win, true); in fimd_update_plane()
884 if (ctx->driver_data->has_shadowcon) in fimd_update_plane()
885 fimd_enable_shadow_channel_path(ctx, win, true); in fimd_update_plane()
887 if (ctx->i80_if) in fimd_update_plane()
888 atomic_set(&ctx->win_updated, 1); in fimd_update_plane()
894 struct fimd_context *ctx = crtc->ctx; in fimd_disable_plane() local
897 if (ctx->suspended) in fimd_disable_plane()
900 fimd_enable_video_output(ctx, win, false); in fimd_disable_plane()
902 if (ctx->driver_data->has_shadowcon) in fimd_disable_plane()
903 fimd_enable_shadow_channel_path(ctx, win, false); in fimd_disable_plane()
908 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_enable() local
910 if (!ctx->suspended) in fimd_atomic_enable()
913 ctx->suspended = false; in fimd_atomic_enable()
915 if (pm_runtime_resume_and_get(ctx->dev) < 0) { in fimd_atomic_enable()
916 dev_warn(ctx->dev, "failed to enable FIMD device.\n"); in fimd_atomic_enable()
921 if (test_and_clear_bit(0, &ctx->irq_flags)) in fimd_atomic_enable()
922 fimd_enable_vblank(ctx->crtc); in fimd_atomic_enable()
924 fimd_commit(ctx->crtc); in fimd_atomic_enable()
929 struct fimd_context *ctx = crtc->ctx; in fimd_atomic_disable() local
932 if (ctx->suspended) in fimd_atomic_disable()
941 fimd_disable_plane(crtc, &ctx->planes[i]); in fimd_atomic_disable()
947 writel(0, ctx->regs + VIDCON0); in fimd_atomic_disable()
949 pm_runtime_put_sync(ctx->dev); in fimd_atomic_disable()
950 ctx->suspended = true; in fimd_atomic_disable()
955 struct fimd_context *ctx = dev_get_drvdata(dev); in fimd_trigger() local
956 const struct fimd_driver_data *driver_data = ctx->driver_data; in fimd_trigger()
957 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_trigger()
964 if (atomic_read(&ctx->triggering)) in fimd_trigger()
968 atomic_set(&ctx->triggering, 1); in fimd_trigger()
978 if (!test_bit(0, &ctx->irq_flags)) in fimd_trigger()
979 atomic_set(&ctx->triggering, 0); in fimd_trigger()
984 struct fimd_context *ctx = crtc->ctx; in fimd_te_handler() local
985 u32 trg_type = ctx->driver_data->trg_type; in fimd_te_handler()
988 if (!ctx->drm_dev) in fimd_te_handler()
998 if (atomic_add_unless(&ctx->win_updated, -1, 0)) in fimd_te_handler()
999 fimd_trigger(ctx->dev); in fimd_te_handler()
1003 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_te_handler()
1004 atomic_set(&ctx->wait_vsync_event, 0); in fimd_te_handler()
1005 wake_up(&ctx->wait_vsync_queue); in fimd_te_handler()
1008 if (test_bit(0, &ctx->irq_flags)) in fimd_te_handler()
1009 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_te_handler()
1014 struct fimd_context *ctx = container_of(clk, struct fimd_context, in fimd_dp_clock_enable() local
1017 writel(val, ctx->regs + DP_MIE_CLKCON); in fimd_dp_clock_enable()
1035 struct fimd_context *ctx = (struct fimd_context *)dev_id; in fimd_irq_handler() local
1038 val = readl(ctx->regs + VIDINTCON1); in fimd_irq_handler()
1040 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; in fimd_irq_handler()
1042 writel(clear_bit, ctx->regs + VIDINTCON1); in fimd_irq_handler()
1045 if (!ctx->drm_dev) in fimd_irq_handler()
1048 if (!ctx->i80_if) in fimd_irq_handler()
1049 drm_crtc_handle_vblank(&ctx->crtc->base); in fimd_irq_handler()
1051 if (ctx->i80_if) { in fimd_irq_handler()
1053 atomic_set(&ctx->triggering, 0); in fimd_irq_handler()
1056 if (atomic_read(&ctx->wait_vsync_event)) { in fimd_irq_handler()
1057 atomic_set(&ctx->wait_vsync_event, 0); in fimd_irq_handler()
1058 wake_up(&ctx->wait_vsync_queue); in fimd_irq_handler()
1068 struct fimd_context *ctx = dev_get_drvdata(dev); in fimd_bind() local
1074 ctx->drm_dev = drm_dev; in fimd_bind()
1077 ctx->configs[i].pixel_formats = fimd_formats; in fimd_bind()
1078 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); in fimd_bind()
1079 ctx->configs[i].zpos = i; in fimd_bind()
1080 ctx->configs[i].type = fimd_win_types[i]; in fimd_bind()
1081 ctx->configs[i].capabilities = capabilities[i]; in fimd_bind()
1082 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, in fimd_bind()
1083 &ctx->configs[i]); in fimd_bind()
1088 exynos_plane = &ctx->planes[DEFAULT_WIN]; in fimd_bind()
1089 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in fimd_bind()
1090 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); in fimd_bind()
1091 if (IS_ERR(ctx->crtc)) in fimd_bind()
1092 return PTR_ERR(ctx->crtc); in fimd_bind()
1094 if (ctx->driver_data->has_dp_clk) { in fimd_bind()
1095 ctx->dp_clk.enable = fimd_dp_clock_enable; in fimd_bind()
1096 ctx->crtc->pipe_clk = &ctx->dp_clk; in fimd_bind()
1099 if (ctx->encoder) in fimd_bind()
1100 exynos_dpi_bind(drm_dev, ctx->encoder); in fimd_bind()
1105 ret = fimd_clear_channels(ctx->crtc); in fimd_bind()
1110 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); in fimd_bind()
1116 struct fimd_context *ctx = dev_get_drvdata(dev); in fimd_unbind() local
1118 fimd_atomic_disable(ctx->crtc); in fimd_unbind()
1120 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); in fimd_unbind()
1122 if (ctx->encoder) in fimd_unbind()
1123 exynos_dpi_remove(ctx->encoder); in fimd_unbind()
1134 struct fimd_context *ctx; in fimd_probe() local
1142 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); in fimd_probe()
1143 if (!ctx) in fimd_probe()
1146 ctx->dev = dev; in fimd_probe()
1147 ctx->suspended = true; in fimd_probe()
1148 ctx->driver_data = of_device_get_match_data(dev); in fimd_probe()
1151 ctx->vidcon1 |= VIDCON1_INV_VDEN; in fimd_probe()
1153 ctx->vidcon1 |= VIDCON1_INV_VCLK; in fimd_probe()
1159 ctx->i80_if = true; in fimd_probe()
1161 if (ctx->driver_data->has_vidoutcon) in fimd_probe()
1162 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; in fimd_probe()
1164 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; in fimd_probe()
1169 ctx->vidcon0 |= VIDCON0_DSI_EN; in fimd_probe()
1173 ctx->i80ifcon = LCD_CS_SETUP(val); in fimd_probe()
1176 ctx->i80ifcon |= LCD_WR_SETUP(val); in fimd_probe()
1179 ctx->i80ifcon |= LCD_WR_ACTIVE(val); in fimd_probe()
1182 ctx->i80ifcon |= LCD_WR_HOLD(val); in fimd_probe()
1186 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, in fimd_probe()
1188 if (IS_ERR(ctx->sysreg)) { in fimd_probe()
1190 ctx->sysreg = NULL; in fimd_probe()
1193 ctx->bus_clk = devm_clk_get(dev, "fimd"); in fimd_probe()
1194 if (IS_ERR(ctx->bus_clk)) { in fimd_probe()
1196 return PTR_ERR(ctx->bus_clk); in fimd_probe()
1199 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); in fimd_probe()
1200 if (IS_ERR(ctx->lcd_clk)) { in fimd_probe()
1202 return PTR_ERR(ctx->lcd_clk); in fimd_probe()
1205 ctx->regs = devm_platform_ioremap_resource(pdev, 0); in fimd_probe()
1206 if (IS_ERR(ctx->regs)) in fimd_probe()
1207 return PTR_ERR(ctx->regs); in fimd_probe()
1210 ctx->i80_if ? "lcd_sys" : "vsync"); in fimd_probe()
1217 0, "drm_fimd", ctx); in fimd_probe()
1223 init_waitqueue_head(&ctx->wait_vsync_queue); in fimd_probe()
1224 atomic_set(&ctx->wait_vsync_event, 0); in fimd_probe()
1226 platform_set_drvdata(pdev, ctx); in fimd_probe()
1228 ctx->encoder = exynos_dpi_probe(dev); in fimd_probe()
1229 if (IS_ERR(ctx->encoder)) in fimd_probe()
1230 return PTR_ERR(ctx->encoder); in fimd_probe()
1258 struct fimd_context *ctx = dev_get_drvdata(dev); in exynos_fimd_suspend() local
1260 clk_disable_unprepare(ctx->lcd_clk); in exynos_fimd_suspend()
1261 clk_disable_unprepare(ctx->bus_clk); in exynos_fimd_suspend()
1268 struct fimd_context *ctx = dev_get_drvdata(dev); in exynos_fimd_resume() local
1271 ret = clk_prepare_enable(ctx->bus_clk); in exynos_fimd_resume()
1279 ret = clk_prepare_enable(ctx->lcd_clk); in exynos_fimd_resume()