Lines Matching refs:lane_value
222 u32 lane_reg, lane_value; in cdv_dpll_set_clock_cdv() local
336 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
337 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
338 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
339 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
342 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
343 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
344 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
345 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
348 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
349 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
350 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
351 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
354 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
355 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
356 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
357 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()