Lines Matching refs:dpll
300 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
312 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
314 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
329 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
341 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
360 const struct dpll *clock) in intel_pll_is_valid()
431 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
432 struct dpll *best_clock) in i9xx_find_best_dpll()
435 struct dpll clock; in i9xx_find_best_dpll()
489 int target, int refclk, struct dpll *match_clock, in pnv_find_best_dpll()
490 struct dpll *best_clock) in pnv_find_best_dpll()
493 struct dpll clock; in pnv_find_best_dpll()
545 int target, int refclk, struct dpll *match_clock, in g4x_find_best_dpll()
546 struct dpll *best_clock) in g4x_find_best_dpll()
549 struct dpll clock; in g4x_find_best_dpll()
596 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
597 const struct dpll *best_clock, in vlv_PLL_is_optimal()
639 int target, int refclk, struct dpll *match_clock, in vlv_find_best_dpll()
640 struct dpll *best_clock) in vlv_find_best_dpll()
644 struct dpll clock; in vlv_find_best_dpll()
699 int target, int refclk, struct dpll *match_clock, in chv_find_best_dpll()
700 struct dpll *best_clock) in chv_find_best_dpll()
705 struct dpll clock; in chv_find_best_dpll()
756 struct dpll *best_clock) in bxt_find_best_dpll()
766 static u32 pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
768 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
773 struct dpll *reduced_clock) in i9xx_update_pll_dividers()
779 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
783 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
800 struct dpll *reduced_clock) in i9xx_compute_dpll()
803 u32 dpll; in i9xx_compute_dpll() local
804 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
808 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
811 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
813 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
817 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
823 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
826 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
830 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
834 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
841 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
851 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
854 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
857 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
859 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
861 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
862 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
873 struct dpll *reduced_clock) in i8xx_compute_dpll()
877 u32 dpll; in i8xx_compute_dpll() local
878 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
882 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
885 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
888 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
890 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
892 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
909 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
913 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
915 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
917 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
918 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
945 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
947 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ilk_needs_fb_cb_tune()
953 struct dpll *reduced_clock) in ilk_compute_dpll()
956 u32 dpll, fp, fp2; in ilk_compute_dpll() local
971 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ilk_compute_dpll()
973 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ilk_compute_dpll()
985 dpll = 0; in ilk_compute_dpll()
988 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
990 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
992 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
997 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1000 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1018 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1021 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1023 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1025 switch (crtc_state->dpll.p2) { in ilk_compute_dpll()
1027 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1030 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1033 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1036 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1042 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1044 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1046 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1048 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1094 refclk, NULL, &crtc_state->dpll)) { in ilk_crtc_compute_clock()
1115 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1118 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1122 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1132 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1135 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1139 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1157 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
1179 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1223 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
1260 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
1297 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
1336 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
1381 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1395 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1396 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1411 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1416 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1476 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1526 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1568 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
1571 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
1576 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
1577 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
1578 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
1579 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
1580 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
1669 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
1672 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
1675 bestn = pipe_config->dpll.n; in chv_prepare_pll()
1676 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1677 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
1678 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
1679 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
1680 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
1681 vco = pipe_config->dpll.vco; in chv_prepare_pll()
1771 const struct dpll *dpll) in vlv_force_pll_on() argument
1782 pipe_config->dpll = *dpll; in vlv_force_pll_on()