115 	enum transcoder trans_shift;  in psr_irq_control()
126 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in psr_irq_control()
128 		trans_shift = intel_dp->psr.transcoder;  in psr_irq_control()
184 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_irq_handler()
187 	enum transcoder trans_shift;  in intel_psr_irq_handler()
192 		imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);  in intel_psr_irq_handler()
194 		trans_shift = intel_dp->psr.transcoder;  in intel_psr_irq_handler()
388 			       EDP_PSR_AUX_DATA(intel_dp->psr.transcoder, i >> 2),  in hsw_psr_setup_aux()
399 	intel_de_write(dev_priv, EDP_PSR_AUX_CTL(intel_dp->psr.transcoder),  in hsw_psr_setup_aux()
510 	val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &  in hsw_activate_psr1()
512 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr1()
604 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),  in hsw_activate_psr2()
608 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
615 	intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);  in hsw_activate_psr2()
617 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in hsw_activate_psr2()
621 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)  in transcoder_has_psr2()
647 	val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));  in psr2_program_idle_frames()
650 	intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in psr2_program_idle_frames()
1111 		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));  in intel_psr_get_config()
1117 		val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));  in intel_psr_get_config()
1128 	enum transcoder transcoder = intel_dp->psr.transcoder;  in intel_psr_activate()  local
1130 	if (transcoder_has_psr2(dev_priv, transcoder))  in intel_psr_activate()
1132 			    intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);  in intel_psr_activate()
1135 		    intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);  in intel_psr_activate()
1151 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;  in intel_psr_enable_source()
1183 	intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1211 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_enable_source()
1231 				    TRANS_PSR_IIR(intel_dp->psr.transcoder));  in psr_interrupt_error_check()
1235 		val &= EDP_PSR_ERROR(intel_dp->psr.transcoder);  in psr_interrupt_error_check()
1262 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;  in intel_psr_enable_locked()
1321 		if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {  in intel_psr_exit()
1323 					    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1328 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1337 				    EDP_PSR2_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1341 			       EDP_PSR2_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1344 				    EDP_PSR_CTL(intel_dp->psr.transcoder));  in intel_psr_exit()
1348 			       EDP_PSR_CTL(intel_dp->psr.transcoder), val);  in intel_psr_exit()
1360 		psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1363 		psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in intel_psr_wait_exit_locked()
1400 			     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),  in intel_psr_disable_locked()
1899 					 EDP_PSR_STATUS(intel_dp->psr.transcoder),  in psr_wait_for_idle()
1951 		reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()
1954 		reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);  in __psr_wait_for_idle_locked()