Lines Matching refs:vgpu_vreg
78 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg()
84 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg()
286 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write()
309 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write()
310 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
321 data = vgpu_vreg(vgpu, offset); in gdrst_mmio_write()
358 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
380 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { in pch_pp_control_mmio_write()
398 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) in transconf_mmio_write()
399 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; in transconf_mmio_write()
401 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; in transconf_mmio_write()
410 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) in lcpll_ctl_mmio_write()
411 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; in lcpll_ctl_mmio_write()
413 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; in lcpll_ctl_mmio_write()
415 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) in lcpll_ctl_mmio_write()
416 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; in lcpll_ctl_mmio_write()
418 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; in lcpll_ctl_mmio_write()
431 vgpu_vreg(vgpu, offset) = 1 << 17; in dpy_reg_mmio_read()
434 vgpu_vreg(vgpu, offset) = 0x3; in dpy_reg_mmio_read()
437 vgpu_vreg(vgpu, offset) = 0x2f << 16; in dpy_reg_mmio_read()
701 data = vgpu_vreg(vgpu, offset); in pipeconf_mmio_write()
704 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; in pipeconf_mmio_write()
708 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; in pipeconf_mmio_write()
796 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { in ddi_buf_ctl_mmio_write()
797 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; in ddi_buf_ctl_mmio_write()
799 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; in ddi_buf_ctl_mmio_write()
810 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; in fdi_rx_iir_mmio_write()
820 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); in fdi_auto_training_started()
952 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; in dp_tp_ctl_mmio_write()
969 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | in dp_tp_status_mmio_write()
970 (vgpu_vreg(vgpu, offset) & sticky_mask); in dp_tp_status_mmio_write()
971 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); in dp_tp_status_mmio_write()
981 data = vgpu_vreg(vgpu, offset); in pch_adpa_mmio_write()
984 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; in pch_adpa_mmio_write()
994 data = vgpu_vreg(vgpu, offset); in south_chicken2_mmio_write()
997 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; in south_chicken2_mmio_write()
999 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; in south_chicken2_mmio_write()
1014 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in pri_surf_mmio_write()
1036 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in spr_surf_mmio_write()
1057 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1060 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1063 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) in reg50080_mmio_write()
1113 vgpu_vreg(vgpu, reg) = value; in dp_aux_ch_ctl_trans_done()
1175 data = vgpu_vreg(vgpu, offset); in dp_aux_ch_ctl_mmio_write()
1189 vgpu_vreg(vgpu, offset) = 0; in dp_aux_ch_ctl_mmio_write()
1197 msg = vgpu_vreg(vgpu, offset + 4); in dp_aux_ch_ctl_mmio_write()
1217 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; in dp_aux_ch_ctl_mmio_write()
1234 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); in dp_aux_ch_ctl_mmio_write()
1256 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1275 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1276 vgpu_vreg(vgpu, offset + 8) = 0; in dp_aux_ch_ctl_mmio_write()
1277 vgpu_vreg(vgpu, offset + 12) = 0; in dp_aux_ch_ctl_mmio_write()
1278 vgpu_vreg(vgpu, offset + 16) = 0; in dp_aux_ch_ctl_mmio_write()
1279 vgpu_vreg(vgpu, offset + 20) = 0; in dp_aux_ch_ctl_mmio_write()
1288 vgpu_vreg(vgpu, offset + 4 * idx) = 0; in dp_aux_ch_ctl_mmio_write()
1310 vgpu_vreg(vgpu, offset + in dp_aux_ch_ctl_mmio_write()
1343 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; in vga_control_mmio_write()
1398 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, in sbi_data_mmio_read()
1411 data = vgpu_vreg(vgpu, offset); in sbi_ctl_mmio_write()
1419 vgpu_vreg(vgpu, offset) = data; in sbi_ctl_mmio_write()
1578 if (vgpu_vreg(vgpu, offset) & in power_well_ctl_mmio_write()
1580 vgpu_vreg(vgpu, offset) |= in power_well_ctl_mmio_write()
1583 vgpu_vreg(vgpu, offset) &= in power_well_ctl_mmio_write()
1593 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) in gen9_dbuf_ctl_mmio_write()
1594 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; in gen9_dbuf_ctl_mmio_write()
1596 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; in gen9_dbuf_ctl_mmio_write()
1606 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) in fpga_dbg_mmio_write()
1607 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; in fpga_dbg_mmio_write()
1618 mode = vgpu_vreg(vgpu, offset); in dma_ctrl_write()
1659 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) in dpll_status_read()
1662 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) in dpll_status_read()
1665 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) in dpll_status_read()
1668 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) in dpll_status_read()
1671 vgpu_vreg(vgpu, offset) = v; in dpll_status_read()
1789 vgpu_vreg(vgpu, offset) = v; in skl_lcpll_write()
1802 vgpu_vreg(vgpu, offset) = v; in bxt_de_pll_enable_write()
1815 vgpu_vreg(vgpu, offset) = v; in bxt_port_pll_enable_write()
1828 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; in bxt_phy_ctl_family_write()
1831 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; in bxt_phy_ctl_family_write()
1832 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; in bxt_phy_ctl_family_write()
1836 vgpu_vreg(vgpu, offset) = v; in bxt_phy_ctl_family_write()
1844 u32 v = vgpu_vreg(vgpu, offset); in bxt_port_tx_dw3_read()
1848 vgpu_vreg(vgpu, offset) = v; in bxt_port_tx_dw3_read()
1859 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1860 vgpu_vreg(vgpu, offset - 0x800) = v; in bxt_pcs_dw12_grp_write()
1862 vgpu_vreg(vgpu, offset - 0x400) = v; in bxt_pcs_dw12_grp_write()
1863 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1866 vgpu_vreg(vgpu, offset) = v; in bxt_pcs_dw12_grp_write()
1891 vgpu_vreg(vgpu, offset) = v; in bxt_gt_disp_pwron_write()
1899 vgpu_vreg(vgpu, offset) = 0; in edp_psr_imr_iir_write()
1926 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); in bxt_ppat_low_write()
1937 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; in guc_status_read()
1960 vgpu_vreg(vgpu, offset) = in mmio_read_from_hw()
2075 vgpu_vreg(vgpu, offset) = 0; in gvt_reg_tlb_control_handler()
2107 data = vgpu_vreg(vgpu, offset); in ring_reset_ctl_write()
2114 vgpu_vreg(vgpu, offset) = data; in ring_reset_ctl_write()
3831 old_vreg = vgpu_vreg(vgpu, offset); in intel_vgpu_mask_mmio_write()
3833 mask = vgpu_vreg(vgpu, offset) >> 16; in intel_vgpu_mask_mmio_write()
3834 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | in intel_vgpu_mask_mmio_write()
3835 (vgpu_vreg(vgpu, offset) & mask); in intel_vgpu_mask_mmio_write()
3909 old_vreg = vgpu_vreg(vgpu, offset); in intel_vgpu_mmio_reg_rw()
3921 data |= vgpu_vreg(vgpu, offset) & ro_mask; in intel_vgpu_mmio_reg_rw()
3927 u32 mask = vgpu_vreg(vgpu, offset) >> 16; in intel_vgpu_mmio_reg_rw()
3929 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) in intel_vgpu_mmio_reg_rw()
3930 | (vgpu_vreg(vgpu, offset) & mask); in intel_vgpu_mmio_reg_rw()
3961 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); in mmio_pm_restore_handler()