1098 	dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;  in g4x_setup_wm_latency()
1099 	dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;  in g4x_setup_wm_latency()
1100 	dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;  in g4x_setup_wm_latency()
1155 	unsigned int latency = dev_priv->wm.pri_latency[level] * 10;  in g4x_compute_wm()
1661 	dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;  in vlv_setup_wm_latency()
1666 		dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;  in vlv_setup_wm_latency()
1667 		dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;  in vlv_setup_wm_latency()
1683 	if (dev_priv->wm.pri_latency[level] == 0)  in vlv_compute_wm_level()
1704 				    dev_priv->wm.pri_latency[level] * 10);  in vlv_compute_wm_level()
2839 	u16 pri_latency = dev_priv->wm.pri_latency[level];  in ilk_compute_wm_level()  local
2845 		pri_latency *= 5;  in ilk_compute_wm_level()
2852 						     pri_latency, level);  in ilk_compute_wm_level()
3066 	changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12);  in snb_wm_latency_quirk()
3075 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);  in snb_wm_latency_quirk()
3093 	if (dev_priv->wm.pri_latency[3] == 0 &&  in snb_wm_lp3_irq_quirk()
3098 	dev_priv->wm.pri_latency[3] = 0;  in snb_wm_lp3_irq_quirk()
3104 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);  in snb_wm_lp3_irq_quirk()
3111 	intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);  in ilk_setup_wm_latency()
3113 	memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,  in ilk_setup_wm_latency()
3114 	       sizeof(dev_priv->wm.pri_latency));  in ilk_setup_wm_latency()
3115 	memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,  in ilk_setup_wm_latency()
3116 	       sizeof(dev_priv->wm.pri_latency));  in ilk_setup_wm_latency()
3121 	intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);  in ilk_setup_wm_latency()
3400 		return dev_priv->wm.pri_latency[level];  in ilk_wm_lp_latency()
8130 		if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&  in intel_init_pm()
8132 		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&  in intel_init_pm()