116 		       const struct i915_request *rq)  in hws_address()  argument
118 	return hws->node.start + seqno_offset(rq->fence.context);  in hws_address()
122 			  struct i915_request *rq,  in move_to_active()  argument
128 	err = i915_request_await_object(rq, vma->obj,  in move_to_active()
131 		err = i915_vma_move_to_active(vma, rq, flags);  in move_to_active()
143 	struct i915_request *rq = NULL;  in igt_spinner_create_request()  local
163 	rq = intel_context_create_request(ce);  in igt_spinner_create_request()
164 	if (IS_ERR(rq))  in igt_spinner_create_request()
165 		return ERR_CAST(rq);  in igt_spinner_create_request()
167 	err = move_to_active(vma, rq, 0);  in igt_spinner_create_request()
171 	err = move_to_active(hws, rq, 0);  in igt_spinner_create_request()
177 	if (GRAPHICS_VER(rq->engine->i915) >= 8) {  in igt_spinner_create_request()
179 		*batch++ = lower_32_bits(hws_address(hws, rq));  in igt_spinner_create_request()
180 		*batch++ = upper_32_bits(hws_address(hws, rq));  in igt_spinner_create_request()
181 	} else if (GRAPHICS_VER(rq->engine->i915) >= 6) {  in igt_spinner_create_request()
184 		*batch++ = hws_address(hws, rq);  in igt_spinner_create_request()
185 	} else if (GRAPHICS_VER(rq->engine->i915) >= 4) {  in igt_spinner_create_request()
188 		*batch++ = hws_address(hws, rq);  in igt_spinner_create_request()
191 		*batch++ = hws_address(hws, rq);  in igt_spinner_create_request()
193 	*batch++ = rq->fence.seqno;  in igt_spinner_create_request()
197 	if (GRAPHICS_VER(rq->engine->i915) >= 8)  in igt_spinner_create_request()
199 	else if (IS_HASWELL(rq->engine->i915))  in igt_spinner_create_request()
201 	else if (GRAPHICS_VER(rq->engine->i915) >= 6)  in igt_spinner_create_request()
213 		err = engine->emit_init_breadcrumb(rq);  in igt_spinner_create_request()
219 	if (GRAPHICS_VER(rq->engine->i915) <= 5)  in igt_spinner_create_request()
221 	err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);  in igt_spinner_create_request()
225 		i915_request_set_error_once(rq, err);  in igt_spinner_create_request()
226 		i915_request_add(rq);  in igt_spinner_create_request()
228 	return err ? ERR_PTR(err) : rq;  in igt_spinner_create_request()
232 hws_seqno(const struct igt_spinner *spin, const struct i915_request *rq)  in hws_seqno()  argument
234 	u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);  in hws_seqno()
265 bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)  in igt_wait_for_spinner()  argument
267 	if (i915_request_is_ready(rq))  in igt_wait_for_spinner()
268 		intel_engine_flush_submission(rq->engine);  in igt_wait_for_spinner()
270 	return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq),  in igt_wait_for_spinner()
271 					       rq->fence.seqno),  in igt_wait_for_spinner()
273 		 wait_for(i915_seqno_passed(hws_seqno(spin, rq),  in igt_wait_for_spinner()
274 					    rq->fence.seqno),  in igt_wait_for_spinner()