90 	u32 control_status;  member
175 	dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |  in dcss_dtg_init()
309 	dtg->control_status |=  in dcss_dtg_css_set()
315 	dtg->control_status |= DTG_START;  in dcss_dtg_enable()
317 	dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_enable()
318 	dtg->control_status |= dtg->alpha_cfg;  in dcss_dtg_enable()
320 	dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_enable()
327 	dtg->control_status &= ~DTG_START;  in dcss_dtg_shutoff()
329 	dcss_writel(dtg->control_status,  in dcss_dtg_shutoff()
343 	u32 control_status;  in dcss_dtg_ch_enable()  local
345 	control_status = dtg->control_status & ~ch_en_map[ch_num];  in dcss_dtg_ch_enable()
346 	control_status |= en ? ch_en_map[ch_num] : 0;  in dcss_dtg_ch_enable()
348 	control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_ch_enable()
349 	control_status |= dtg->alpha_cfg;  in dcss_dtg_ch_enable()
351 	if (dtg->control_status != control_status)  in dcss_dtg_ch_enable()
352 		dcss_dtg_write(dtg, control_status, DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_ch_enable()
354 	dtg->control_status = control_status;  in dcss_dtg_ch_enable()