25 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,  in zap_shader_load_mdt()  argument
28 	struct device *dev = &gpu->pdev->dev;  in zap_shader_load_mdt()
80 		ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);  in zap_shader_load_mdt()
85 		fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);  in zap_shader_load_mdt()
135 	if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {  in zap_shader_load_mdt()
171 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)  in adreno_zap_shader_load()  argument
173 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_zap_shader_load()
174 	struct platform_device *pdev = gpu->pdev;  in adreno_zap_shader_load()
186 	return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);  in adreno_zap_shader_load()
195 adreno_iommu_create_address_space(struct msm_gpu *gpu,  in adreno_iommu_create_address_space()  argument
230 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)  in adreno_get_param()  argument
232 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_get_param()
257 			pm_runtime_get_sync(&gpu->pdev->dev);  in adreno_get_param()
258 			ret = adreno_gpu->funcs->get_timestamp(gpu, value);  in adreno_get_param()
259 			pm_runtime_put_autosuspend(&gpu->pdev->dev);  in adreno_get_param()
265 		*value = gpu->nr_rings * NR_SCHED_PRIORITIES;  in adreno_get_param()
271 		*value = gpu->global_faults;  in adreno_get_param()
274 		*value = gpu->suspend_count;  in adreno_get_param()
277 		DBG("%s: invalid param: %u", gpu->name, param);  in adreno_get_param()
387 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,  in adreno_fw_create_bo()  argument
393 	ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,  in adreno_fw_create_bo()
394 		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);  in adreno_fw_create_bo()
406 int adreno_hw_init(struct msm_gpu *gpu)  in adreno_hw_init()  argument
408 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_hw_init()
411 	VERB("%s", gpu->name);  in adreno_hw_init()
417 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_hw_init()
418 		struct msm_ringbuffer *ring = gpu->rb[i];  in adreno_hw_init()
438 	struct msm_gpu *gpu = &adreno_gpu->base;  in get_rptr()  local
440 	return gpu->funcs->get_rptr(gpu, ring);  in get_rptr()
443 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)  in adreno_active_ring()  argument
445 	return gpu->rb[0];  in adreno_active_ring()
448 void adreno_recover(struct msm_gpu *gpu)  in adreno_recover()  argument
450 	struct drm_device *dev = gpu->dev;  in adreno_recover()
456 	gpu->funcs->pm_suspend(gpu);  in adreno_recover()
457 	gpu->funcs->pm_resume(gpu);  in adreno_recover()
459 	ret = msm_gpu_hw_init(gpu);  in adreno_recover()
466 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)  in adreno_flush()  argument
483 	gpu_write(gpu, reg, wptr);  in adreno_flush()
486 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in adreno_idle()  argument
488 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_idle()
497 		gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);  in adreno_idle()
502 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)  in adreno_gpu_state_get()  argument
504 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_gpu_state_get()
511 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_gpu_state_get()
514 		state->ring[i].fence = gpu->rb[i]->memptrs->fence;  in adreno_gpu_state_get()
515 		state->ring[i].iova = gpu->rb[i]->iova;  in adreno_gpu_state_get()
516 		state->ring[i].seqno = gpu->rb[i]->seqno;  in adreno_gpu_state_get()
517 		state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);  in adreno_gpu_state_get()
518 		state->ring[i].wptr = get_wptr(gpu->rb[i]);  in adreno_gpu_state_get()
525 			if (gpu->rb[i]->start[j])  in adreno_gpu_state_get()
531 				memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);  in adreno_gpu_state_get()
557 				state->registers[pos++] = gpu_read(gpu, addr);  in adreno_gpu_state_get()
674 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,  in adreno_show()  argument
677 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_show()
707 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_show()
751 void adreno_dump_info(struct msm_gpu *gpu)  in adreno_dump_info()  argument
753 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_dump_info()
761 	for (i = 0; i < gpu->nr_rings; i++) {  in adreno_dump_info()
762 		struct msm_ringbuffer *ring = gpu->rb[i];  in adreno_dump_info()
774 void adreno_dump(struct msm_gpu *gpu)  in adreno_dump()  argument
776 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in adreno_dump()
783 	printk("IO:region %s 00000000 00020000\n", gpu->name);  in adreno_dump()
790 			uint32_t val = gpu_read(gpu, addr);  in adreno_dump()
798 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);  in ring_freewords()
809 		DRM_DEV_ERROR(ring->gpu->dev->dev,  in adreno_wait_ring()
847 		struct msm_gpu *gpu)  in adreno_get_pwrlevels()  argument
853 	gpu->fast_rate = 0;  in adreno_get_pwrlevels()
868 			gpu->fast_rate = freq;  in adreno_get_pwrlevels()
873 	if (!gpu->fast_rate) {  in adreno_get_pwrlevels()
877 		gpu->fast_rate = 200000000;  in adreno_get_pwrlevels()
880 	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);  in adreno_get_pwrlevels()
929 	struct msm_gpu *gpu = &adreno_gpu->base;  in adreno_gpu_init()  local
941 	adreno_get_pwrlevels(dev, gpu);  in adreno_gpu_init()
953 	struct msm_gpu *gpu = &adreno_gpu->base;  in adreno_gpu_cleanup()  local
954 	struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL;  in adreno_gpu_cleanup()