103 static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,  in pll_get_cpctrl()  argument
106 	if ((frac_start != 0) || gen_ssc)  in pll_get_cpctrl()
112 static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)  in pll_get_rctrl()  argument
114 	if ((frac_start != 0) || gen_ssc)  in pll_get_rctrl()
120 static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)  in pll_get_cctrl()  argument
122 	if ((frac_start != 0) || gen_ssc)  in pll_get_cctrl()
128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,  in pll_get_integloop_gain()  argument
134 	if ((frac_start != 0) || gen_ssc)  in pll_get_integloop_gain()
225 	u64 frac_start;  in pll_calculate()  local
252 	frac_start = pd.vco_freq * (1 << 20);  in pll_calculate()
254 	rem = do_div(frac_start, pll_divisor);  in pll_calculate()
255 	frac_start -= dec_start * (1 << 20);  in pll_calculate()
257 		frac_start++;  in pll_calculate()
259 	cpctrl = pll_get_cpctrl(frac_start, ref_clk, false);  in pll_calculate()
260 	rctrl = pll_get_rctrl(frac_start, false);  in pll_calculate()
261 	cctrl = pll_get_cctrl(frac_start, false);  in pll_calculate()
262 	integloop_gain = pll_get_integloop_gain(frac_start, bclk,  in pll_calculate()
276 	DBG("DIV_FRAC_START: %llu", frac_start);  in pll_calculate()
295 	cfg->com_div_frac_start1_mode0 = (frac_start & 0xff);  in pll_calculate()
296 	cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8);  in pll_calculate()
297 	cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);  in pll_calculate()