Lines Matching refs:lt
52 nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay) in nvkm_dp_train_sense() argument
54 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_sense()
62 ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6); in nvkm_dp_train_sense()
67 ret = nvkm_rdaux(dp->aux, DPCD_LS0C, <->pc2stat, 1); in nvkm_dp_train_sense()
69 lt->pc2stat = 0x00; in nvkm_dp_train_sense()
71 lt->stat, lt->pc2stat); in nvkm_dp_train_sense()
73 OUTP_TRACE(&dp->outp, "status %6ph", lt->stat); in nvkm_dp_train_sense()
80 nvkm_dp_train_drive(struct lt_state *lt, bool pc) in nvkm_dp_train_drive() argument
82 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_drive()
92 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_drive()
93 u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3; in nvkm_dp_train_drive()
110 lt->conf[i] = (lpre << 3) | lvsw; in nvkm_dp_train_drive()
111 lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); in nvkm_dp_train_drive()
114 i, lt->conf[i], lpc2); in nvkm_dp_train_drive()
132 ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4); in nvkm_dp_train_drive()
137 ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2); in nvkm_dp_train_drive()
146 nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern) in nvkm_dp_train_pattern() argument
148 struct nvkm_dp *dp = lt->dp; in nvkm_dp_train_pattern()
161 nvkm_dp_train_eq(struct lt_state *lt) in nvkm_dp_train_eq() argument
166 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
167 nvkm_dp_train_pattern(lt, 3); in nvkm_dp_train_eq()
169 nvkm_dp_train_pattern(lt, 2); in nvkm_dp_train_eq()
173 nvkm_dp_train_drive(lt, lt->pc2)) || in nvkm_dp_train_eq()
174 nvkm_dp_train_sense(lt, lt->pc2, 400)) in nvkm_dp_train_eq()
177 eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); in nvkm_dp_train_eq()
178 for (i = 0; i < lt->dp->outp.ior->dp.nr && eq_done; i++) { in nvkm_dp_train_eq()
179 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_eq()
192 nvkm_dp_train_cr(struct lt_state *lt) in nvkm_dp_train_cr() argument
195 int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; in nvkm_dp_train_cr()
198 nvkm_dp_train_pattern(lt, 1); in nvkm_dp_train_cr()
201 if (nvkm_dp_train_drive(lt, false) || in nvkm_dp_train_cr()
202 nvkm_dp_train_sense(lt, false, 100)) in nvkm_dp_train_cr()
206 for (i = 0; i < lt->dp->outp.ior->dp.nr; i++) { in nvkm_dp_train_cr()
207 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in nvkm_dp_train_cr()
210 if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED) in nvkm_dp_train_cr()
216 if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { in nvkm_dp_train_cr()
217 voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; in nvkm_dp_train_cr()
232 struct lt_state lt = { in nvkm_dp_train_links() local
245 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
247 if (AMPERE_IED_HACK(disp) && (lnkcmp = lt.dp->info.script[0])) { in nvkm_dp_train_links()
261 if ((lnkcmp = lt.dp->info.lnkcmp)) { in nvkm_dp_train_links()
301 memset(lt.stat, 0x00, sizeof(lt.stat)); in nvkm_dp_train_links()
302 ret = nvkm_dp_train_cr(<); in nvkm_dp_train_links()
304 ret = nvkm_dp_train_eq(<); in nvkm_dp_train_links()
305 nvkm_dp_train_pattern(<, 0); in nvkm_dp_train_links()
426 ior->dp.mst = dp->lt.mst; in nvkm_dp_train()
439 atomic_set(&dp->lt.done, 1); in nvkm_dp_train()
462 atomic_set(&dp->lt.done, 0); in nvkm_dp_release()
492 dataKBps, linkKBps, ior->dp.mst, dp->lt.mst); in nvkm_dp_acquire()
493 if (linkKBps < dataKBps || ior->dp.mst != dp->lt.mst) { in nvkm_dp_acquire()
523 if (retrain || !atomic_read(&dp->lt.done)) in nvkm_dp_acquire()
552 atomic_set(&dp->lt.done, 0); in nvkm_dp_enable()
567 if (atomic_read(&dp->lt.done)) in nvkm_dp_hpd()
696 atomic_set(&dp->lt.done, 0); in nvkm_dp_ctor()