46 	struct nvkm_head *head;  in gv100_disp_super()  local
51 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
52 		mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4));  in gv100_disp_super()
53 		HEAD_DBG(head, "%08x", mask[head->id]);  in gv100_disp_super()
59 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
60 			if (!(mask[head->id] & 0x00001000))  in gv100_disp_super()
62 			nv50_disp_super_1_0(disp, head);  in gv100_disp_super()
66 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
67 			if (!(mask[head->id] & 0x00001000))  in gv100_disp_super()
69 			nv50_disp_super_2_0(disp, head);  in gv100_disp_super()
72 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
73 			if (!(mask[head->id] & 0x00010000))  in gv100_disp_super()
75 			nv50_disp_super_2_1(disp, head);  in gv100_disp_super()
77 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
78 			if (!(mask[head->id] & 0x00001000))  in gv100_disp_super()
80 			nv50_disp_super_2_2(disp, head);  in gv100_disp_super()
84 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
85 			if (!(mask[head->id] & 0x00001000))  in gv100_disp_super()
87 			nv50_disp_super_3_0(disp, head);  in gv100_disp_super()
91 	list_for_each_entry(head, &disp->base.head, head)  in gv100_disp_super()
92 		nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000);  in gv100_disp_super()
193 	int head;  in gv100_disp_intr_exc_other()  local
202 		for_each_set_bit(head, &mask, disp->wndw.nr) {  in gv100_disp_intr_exc_other()
203 			nvkm_wr32(device, 0x611854, 0x00010000 << head);  in gv100_disp_intr_exc_other()
204 			gv100_disp_exception(disp, 73 + head);  in gv100_disp_intr_exc_other()
205 			stat &= ~(0x00010000 << head);  in gv100_disp_intr_exc_other()
256 gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)  in gv100_disp_intr_head_timing()  argument
260 	u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04));  in gv100_disp_intr_head_timing()
264 		nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003);  in gv100_disp_intr_head_timing()
269 		nvkm_disp_vblank(&disp->base, head);  in gv100_disp_intr_head_timing()
270 		nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004);  in gv100_disp_intr_head_timing()
276 		nvkm_wr32(device, 0x611800 + (head * 0x04), stat);  in gv100_disp_intr_head_timing()
287 	int head;  in gv100_disp_intr()  local
290 		for_each_set_bit(head, &mask, 8) {  in gv100_disp_intr()
291 			gv100_disp_intr_head_timing(disp, head);  in gv100_disp_intr()
292 			stat &= ~BIT(head);  in gv100_disp_intr()
331 	struct nvkm_head *head;  in gv100_disp_init()  local
357 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()
358 		const int id = head->id;  in gv100_disp_init()
404 	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |  in gv100_disp_init()
417 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()
418 		const u32 hoff = head->id * 4;  in gv100_disp_init()
438 	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },