Lines Matching refs:dispc
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
100 int (*calc_scaling)(struct dispc_device *dispc,
342 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
344 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
346 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
349 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
351 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
354 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg() argument
356 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
359 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) in dispc_read_reg() argument
361 return __raw_readl(dispc->base + idx); in dispc_read_reg()
364 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_read() argument
369 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
372 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_write() argument
377 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
380 int dispc_get_num_ovls(struct dispc_device *dispc) in dispc_get_num_ovls() argument
382 return dispc->feat->num_ovls; in dispc_get_num_ovls()
385 int dispc_get_num_mgrs(struct dispc_device *dispc) in dispc_get_num_mgrs() argument
387 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
390 static void dispc_get_reg_field(struct dispc_device *dispc, in dispc_get_reg_field() argument
394 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
396 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
397 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
400 static bool dispc_has_feature(struct dispc_device *dispc, in dispc_has_feature() argument
405 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
406 if (dispc->feat->features[i] == id) in dispc_has_feature()
413 #define SR(dispc, reg) \ argument
414 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
415 #define RR(dispc, reg) \ argument
416 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
418 static void dispc_save_context(struct dispc_device *dispc) in dispc_save_context() argument
424 SR(dispc, IRQENABLE); in dispc_save_context()
425 SR(dispc, CONTROL); in dispc_save_context()
426 SR(dispc, CONFIG); in dispc_save_context()
427 SR(dispc, LINE_NUMBER); in dispc_save_context()
428 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_save_context()
429 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_save_context()
430 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
431 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_save_context()
432 SR(dispc, CONTROL2); in dispc_save_context()
433 SR(dispc, CONFIG2); in dispc_save_context()
435 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_save_context()
436 SR(dispc, CONTROL3); in dispc_save_context()
437 SR(dispc, CONFIG3); in dispc_save_context()
440 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_save_context()
441 SR(dispc, DEFAULT_COLOR(i)); in dispc_save_context()
442 SR(dispc, TRANS_COLOR(i)); in dispc_save_context()
443 SR(dispc, SIZE_MGR(i)); in dispc_save_context()
446 SR(dispc, TIMING_H(i)); in dispc_save_context()
447 SR(dispc, TIMING_V(i)); in dispc_save_context()
448 SR(dispc, POL_FREQ(i)); in dispc_save_context()
449 SR(dispc, DIVISORo(i)); in dispc_save_context()
451 SR(dispc, DATA_CYCLE1(i)); in dispc_save_context()
452 SR(dispc, DATA_CYCLE2(i)); in dispc_save_context()
453 SR(dispc, DATA_CYCLE3(i)); in dispc_save_context()
455 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_save_context()
456 SR(dispc, CPR_COEF_R(i)); in dispc_save_context()
457 SR(dispc, CPR_COEF_G(i)); in dispc_save_context()
458 SR(dispc, CPR_COEF_B(i)); in dispc_save_context()
462 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_save_context()
463 SR(dispc, OVL_BA0(i)); in dispc_save_context()
464 SR(dispc, OVL_BA1(i)); in dispc_save_context()
465 SR(dispc, OVL_POSITION(i)); in dispc_save_context()
466 SR(dispc, OVL_SIZE(i)); in dispc_save_context()
467 SR(dispc, OVL_ATTRIBUTES(i)); in dispc_save_context()
468 SR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_save_context()
469 SR(dispc, OVL_ROW_INC(i)); in dispc_save_context()
470 SR(dispc, OVL_PIXEL_INC(i)); in dispc_save_context()
471 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_save_context()
472 SR(dispc, OVL_PRELOAD(i)); in dispc_save_context()
474 SR(dispc, OVL_WINDOW_SKIP(i)); in dispc_save_context()
475 SR(dispc, OVL_TABLE_BA(i)); in dispc_save_context()
478 SR(dispc, OVL_FIR(i)); in dispc_save_context()
479 SR(dispc, OVL_PICTURE_SIZE(i)); in dispc_save_context()
480 SR(dispc, OVL_ACCU0(i)); in dispc_save_context()
481 SR(dispc, OVL_ACCU1(i)); in dispc_save_context()
484 SR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_save_context()
487 SR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_save_context()
490 SR(dispc, OVL_CONV_COEF(i, j)); in dispc_save_context()
492 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_save_context()
494 SR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_save_context()
497 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_save_context()
498 SR(dispc, OVL_BA0_UV(i)); in dispc_save_context()
499 SR(dispc, OVL_BA1_UV(i)); in dispc_save_context()
500 SR(dispc, OVL_FIR2(i)); in dispc_save_context()
501 SR(dispc, OVL_ACCU2_0(i)); in dispc_save_context()
502 SR(dispc, OVL_ACCU2_1(i)); in dispc_save_context()
505 SR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_save_context()
508 SR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_save_context()
511 SR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_save_context()
513 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_save_context()
514 SR(dispc, OVL_ATTRIBUTES2(i)); in dispc_save_context()
517 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_save_context()
518 SR(dispc, DIVISOR); in dispc_save_context()
520 dispc->ctx_valid = true; in dispc_save_context()
525 static void dispc_restore_context(struct dispc_device *dispc) in dispc_restore_context() argument
531 if (!dispc->ctx_valid) in dispc_restore_context()
536 RR(dispc, CONFIG); in dispc_restore_context()
537 RR(dispc, LINE_NUMBER); in dispc_restore_context()
538 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_restore_context()
539 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_restore_context()
540 RR(dispc, GLOBAL_ALPHA); in dispc_restore_context()
541 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
542 RR(dispc, CONFIG2); in dispc_restore_context()
543 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
544 RR(dispc, CONFIG3); in dispc_restore_context()
546 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_restore_context()
547 RR(dispc, DEFAULT_COLOR(i)); in dispc_restore_context()
548 RR(dispc, TRANS_COLOR(i)); in dispc_restore_context()
549 RR(dispc, SIZE_MGR(i)); in dispc_restore_context()
552 RR(dispc, TIMING_H(i)); in dispc_restore_context()
553 RR(dispc, TIMING_V(i)); in dispc_restore_context()
554 RR(dispc, POL_FREQ(i)); in dispc_restore_context()
555 RR(dispc, DIVISORo(i)); in dispc_restore_context()
557 RR(dispc, DATA_CYCLE1(i)); in dispc_restore_context()
558 RR(dispc, DATA_CYCLE2(i)); in dispc_restore_context()
559 RR(dispc, DATA_CYCLE3(i)); in dispc_restore_context()
561 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_restore_context()
562 RR(dispc, CPR_COEF_R(i)); in dispc_restore_context()
563 RR(dispc, CPR_COEF_G(i)); in dispc_restore_context()
564 RR(dispc, CPR_COEF_B(i)); in dispc_restore_context()
568 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_restore_context()
569 RR(dispc, OVL_BA0(i)); in dispc_restore_context()
570 RR(dispc, OVL_BA1(i)); in dispc_restore_context()
571 RR(dispc, OVL_POSITION(i)); in dispc_restore_context()
572 RR(dispc, OVL_SIZE(i)); in dispc_restore_context()
573 RR(dispc, OVL_ATTRIBUTES(i)); in dispc_restore_context()
574 RR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_restore_context()
575 RR(dispc, OVL_ROW_INC(i)); in dispc_restore_context()
576 RR(dispc, OVL_PIXEL_INC(i)); in dispc_restore_context()
577 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_restore_context()
578 RR(dispc, OVL_PRELOAD(i)); in dispc_restore_context()
580 RR(dispc, OVL_WINDOW_SKIP(i)); in dispc_restore_context()
581 RR(dispc, OVL_TABLE_BA(i)); in dispc_restore_context()
584 RR(dispc, OVL_FIR(i)); in dispc_restore_context()
585 RR(dispc, OVL_PICTURE_SIZE(i)); in dispc_restore_context()
586 RR(dispc, OVL_ACCU0(i)); in dispc_restore_context()
587 RR(dispc, OVL_ACCU1(i)); in dispc_restore_context()
590 RR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_restore_context()
593 RR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_restore_context()
596 RR(dispc, OVL_CONV_COEF(i, j)); in dispc_restore_context()
598 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_restore_context()
600 RR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_restore_context()
603 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_restore_context()
604 RR(dispc, OVL_BA0_UV(i)); in dispc_restore_context()
605 RR(dispc, OVL_BA1_UV(i)); in dispc_restore_context()
606 RR(dispc, OVL_FIR2(i)); in dispc_restore_context()
607 RR(dispc, OVL_ACCU2_0(i)); in dispc_restore_context()
608 RR(dispc, OVL_ACCU2_1(i)); in dispc_restore_context()
611 RR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_restore_context()
614 RR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_restore_context()
617 RR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_restore_context()
619 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_restore_context()
620 RR(dispc, OVL_ATTRIBUTES2(i)); in dispc_restore_context()
623 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_restore_context()
624 RR(dispc, DIVISOR); in dispc_restore_context()
627 RR(dispc, CONTROL); in dispc_restore_context()
628 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
629 RR(dispc, CONTROL2); in dispc_restore_context()
630 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
631 RR(dispc, CONTROL3); in dispc_restore_context()
633 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); in dispc_restore_context()
639 RR(dispc, IRQENABLE); in dispc_restore_context()
647 int dispc_runtime_get(struct dispc_device *dispc) in dispc_runtime_get() argument
653 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
655 pm_runtime_put_noidle(&dispc->pdev->dev); in dispc_runtime_get()
661 void dispc_runtime_put(struct dispc_device *dispc) in dispc_runtime_put() argument
667 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
671 u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, in dispc_mgr_get_vsync_irq() argument
677 u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, in dispc_mgr_get_framedone_irq() argument
680 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
686 u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, in dispc_mgr_get_sync_lost_irq() argument
692 u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) in dispc_wb_get_framedone_irq() argument
697 void dispc_mgr_enable(struct dispc_device *dispc, in dispc_mgr_enable() argument
700 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); in dispc_mgr_enable()
702 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_enable()
705 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, in dispc_mgr_is_enabled() argument
708 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_is_enabled()
711 bool dispc_mgr_go_busy(struct dispc_device *dispc, in dispc_mgr_go_busy() argument
714 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; in dispc_mgr_go_busy()
717 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) in dispc_mgr_go() argument
719 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); in dispc_mgr_go()
720 WARN_ON(dispc_mgr_go_busy(dispc, channel)); in dispc_mgr_go()
724 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); in dispc_mgr_go()
727 bool dispc_wb_go_busy(struct dispc_device *dispc) in dispc_wb_go_busy() argument
729 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
732 void dispc_wb_go(struct dispc_device *dispc) in dispc_wb_go() argument
737 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
742 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
748 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
751 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, in dispc_ovl_write_firh_reg() argument
755 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); in dispc_ovl_write_firh_reg()
758 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv_reg() argument
762 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); in dispc_ovl_write_firhv_reg()
765 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, in dispc_ovl_write_firv_reg() argument
769 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); in dispc_ovl_write_firv_reg()
772 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, in dispc_ovl_write_firh2_reg() argument
778 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); in dispc_ovl_write_firh2_reg()
781 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv2_reg() argument
787 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); in dispc_ovl_write_firhv2_reg()
790 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firv2_reg() argument
796 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); in dispc_ovl_write_firv2_reg()
799 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, in dispc_ovl_set_scale_coef() argument
811 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
829 dispc_ovl_write_firh_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
830 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
832 dispc_ovl_write_firh2_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
833 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
844 dispc_ovl_write_firv_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
846 dispc_ovl_write_firv2_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
861 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, in dispc_ovl_write_color_conv_coef() argument
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
871 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
873 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
910 static void dispc_ovl_set_csc(struct dispc_device *dispc, in dispc_ovl_set_csc() argument
933 dispc_ovl_write_color_conv_coef(dispc, plane, csc); in dispc_ovl_set_csc()
936 static void dispc_ovl_set_ba0(struct dispc_device *dispc, in dispc_ovl_set_ba0() argument
939 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); in dispc_ovl_set_ba0()
942 static void dispc_ovl_set_ba1(struct dispc_device *dispc, in dispc_ovl_set_ba1() argument
945 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); in dispc_ovl_set_ba1()
948 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, in dispc_ovl_set_ba0_uv() argument
951 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); in dispc_ovl_set_ba0_uv()
954 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, in dispc_ovl_set_ba1_uv() argument
957 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); in dispc_ovl_set_ba1_uv()
960 static void dispc_ovl_set_pos(struct dispc_device *dispc, in dispc_ovl_set_pos() argument
971 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); in dispc_ovl_set_pos()
974 static void dispc_ovl_set_input_size(struct dispc_device *dispc, in dispc_ovl_set_input_size() argument
981 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_input_size()
983 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_input_size()
986 static void dispc_ovl_set_output_size(struct dispc_device *dispc, in dispc_ovl_set_output_size() argument
997 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_output_size()
999 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_output_size()
1002 static void dispc_ovl_set_zorder(struct dispc_device *dispc, in dispc_ovl_set_zorder() argument
1009 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1012 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) in dispc_ovl_enable_zorder_planes() argument
1016 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_ovl_enable_zorder_planes()
1019 for (i = 0; i < dispc_get_num_ovls(dispc); i++) in dispc_ovl_enable_zorder_planes()
1020 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1023 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, in dispc_ovl_set_pre_mult_alpha() argument
1031 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1034 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, in dispc_ovl_setup_global_alpha() argument
1046 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1049 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, in dispc_ovl_set_pix_inc() argument
1052 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); in dispc_ovl_set_pix_inc()
1055 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, in dispc_ovl_set_row_inc() argument
1058 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); in dispc_ovl_set_row_inc()
1061 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, in dispc_ovl_set_color_mode() argument
1131 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1134 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, in dispc_ovl_configure_burst_type() argument
1138 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) in dispc_ovl_configure_burst_type()
1142 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
1144 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
1147 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, in dispc_ovl_set_channel_out() argument
1169 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_channel_out()
1170 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_ovl_set_channel_out()
1185 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_ovl_set_channel_out()
1207 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_channel_out()
1210 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, in dispc_ovl_get_channel_out() argument
1230 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_get_channel_out()
1235 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_ovl_get_channel_out()
1251 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, in dispc_ovl_set_burst_size() argument
1259 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, in dispc_ovl_set_burst_size()
1263 static void dispc_configure_burst_sizes(struct dispc_device *dispc) in dispc_configure_burst_sizes() argument
1269 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_configure_burst_sizes()
1270 dispc_ovl_set_burst_size(dispc, i, burst_size); in dispc_configure_burst_sizes()
1271 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1272 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); in dispc_configure_burst_sizes()
1275 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, in dispc_ovl_get_burst_size() argument
1279 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1282 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, in dispc_ovl_color_mode_supported() argument
1288 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1298 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, in dispc_ovl_get_color_modes() argument
1301 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1304 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, in dispc_mgr_enable_cpr() argument
1310 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); in dispc_mgr_enable_cpr()
1313 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, in dispc_mgr_set_cpr_coef() argument
1329 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); in dispc_mgr_set_cpr_coef()
1330 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); in dispc_mgr_set_cpr_coef()
1331 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); in dispc_mgr_set_cpr_coef()
1334 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, in dispc_ovl_set_vid_color_conv() argument
1341 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_vid_color_conv()
1343 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_vid_color_conv()
1346 static void dispc_ovl_enable_replication(struct dispc_device *dispc, in dispc_ovl_enable_replication() argument
1358 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); in dispc_ovl_enable_replication()
1361 static void dispc_mgr_set_size(struct dispc_device *dispc, in dispc_mgr_set_size() argument
1366 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1367 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1369 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); in dispc_mgr_set_size()
1372 static void dispc_init_fifos(struct dispc_device *dispc) in dispc_init_fifos() argument
1380 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1382 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); in dispc_init_fifos()
1384 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1385 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1388 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1394 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1404 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1407 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); in dispc_init_fifos()
1414 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); in dispc_init_fifos()
1416 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1417 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1423 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_fifos()
1428 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, in dispc_init_fifos()
1431 dispc_ovl_set_fifo_threshold(dispc, i, low, high); in dispc_init_fifos()
1434 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1439 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, in dispc_init_fifos()
1443 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_fifos()
1447 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, in dispc_ovl_get_fifo_size() argument
1453 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1454 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1455 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1461 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, in dispc_ovl_set_fifo_threshold() argument
1468 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1476 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1478 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1483 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1485 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1489 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1498 if (dispc_has_feature(dispc, FEAT_PRELOAD) && in dispc_ovl_set_fifo_threshold()
1499 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1500 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), in dispc_ovl_set_fifo_threshold()
1504 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) in dispc_enable_fifomerge() argument
1506 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { in dispc_enable_fifomerge()
1512 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
1515 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, in dispc_ovl_compute_fifo_thresholds() argument
1524 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1528 burst_size = dispc_ovl_get_burst_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1529 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1533 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_ovl_compute_fifo_thresholds()
1534 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); in dispc_ovl_compute_fifo_thresholds()
1545 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { in dispc_ovl_compute_fifo_thresholds()
1562 static void dispc_ovl_set_mflag(struct dispc_device *dispc, in dispc_ovl_set_mflag() argument
1572 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); in dispc_ovl_set_mflag()
1575 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, in dispc_ovl_set_mflag_threshold() argument
1579 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), in dispc_ovl_set_mflag_threshold()
1583 static void dispc_init_mflag(struct dispc_device *dispc) in dispc_init_mflag() argument
1597 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, in dispc_init_mflag()
1601 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_mflag()
1602 u32 size = dispc_ovl_get_fifo_size(dispc, i); in dispc_init_mflag()
1603 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1606 dispc_ovl_set_mflag(dispc, i, true); in dispc_init_mflag()
1617 dispc_ovl_set_mflag_threshold(dispc, i, low, high); in dispc_init_mflag()
1620 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1621 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); in dispc_init_mflag()
1622 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1625 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); in dispc_init_mflag()
1636 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_mflag()
1640 static void dispc_ovl_set_fir(struct dispc_device *dispc, in dispc_ovl_set_fir() argument
1650 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, in dispc_ovl_set_fir()
1652 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, in dispc_ovl_set_fir()
1657 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); in dispc_ovl_set_fir()
1660 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); in dispc_ovl_set_fir()
1664 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu0() argument
1671 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu0()
1673 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu0()
1679 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); in dispc_ovl_set_vid_accu0()
1682 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu1() argument
1689 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu1()
1691 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu1()
1697 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); in dispc_ovl_set_vid_accu1()
1700 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_0() argument
1707 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); in dispc_ovl_set_vid_accu2_0()
1710 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_1() argument
1717 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); in dispc_ovl_set_vid_accu2_1()
1720 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, in dispc_ovl_set_scale_param() argument
1732 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, in dispc_ovl_set_scale_param()
1734 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); in dispc_ovl_set_scale_param()
1737 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, in dispc_ovl_set_accu_uv() argument
1822 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); in dispc_ovl_set_accu_uv()
1823 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); in dispc_ovl_set_accu_uv()
1826 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, in dispc_ovl_set_scaling_common() argument
1838 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_common()
1841 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_scaling_common()
1850 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { in dispc_ovl_set_scaling_common()
1857 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { in dispc_ovl_set_scaling_common()
1862 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_ovl_set_scaling_common()
1877 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); in dispc_ovl_set_scaling_common()
1878 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); in dispc_ovl_set_scaling_common()
1881 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, in dispc_ovl_set_scaling_uv() argument
1896 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) in dispc_ovl_set_scaling_uv()
1902 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1907 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, in dispc_ovl_set_scaling_uv()
1950 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_uv()
1955 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1959 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); in dispc_ovl_set_scaling_uv()
1961 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); in dispc_ovl_set_scaling_uv()
1964 static void dispc_ovl_set_scaling(struct dispc_device *dispc, in dispc_ovl_set_scaling() argument
1974 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1978 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1983 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, in dispc_ovl_set_rotation_attrs() argument
2040 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); in dispc_ovl_set_rotation_attrs()
2041 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) in dispc_ovl_set_rotation_attrs()
2042 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2045 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { in dispc_ovl_set_rotation_attrs()
2052 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2289 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_24xx() argument
2303 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2310 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2313 *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_24xx()
2338 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_34xx() argument
2351 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2368 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2382 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_34xx()
2426 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_44xx() argument
2440 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2441 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2446 in_width_max = dispc_core_clk_rate(dispc) in dispc_ovl_calc_scaling_44xx()
2485 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2493 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, in dispc_ovl_calc_scaling() argument
2505 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2506 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2514 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2515 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2554 dispc_has_feature(dispc, FEAT_BURST_2D)) ? in dispc_ovl_calc_scaling()
2567 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2587 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2589 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { in dispc_ovl_calc_scaling()
2593 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2602 static int dispc_ovl_setup_common(struct dispc_device *dispc, in dispc_ovl_setup_common() argument
2629 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); in dispc_ovl_setup_common()
2630 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); in dispc_ovl_setup_common()
2665 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) in dispc_ovl_setup_common()
2668 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, in dispc_ovl_setup_common()
2730 dispc_ovl_set_color_mode(dispc, plane, fourcc); in dispc_ovl_setup_common()
2732 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); in dispc_ovl_setup_common()
2734 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2737 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); in dispc_ovl_setup_common()
2738 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); in dispc_ovl_setup_common()
2741 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); in dispc_ovl_setup_common()
2742 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); in dispc_ovl_setup_common()
2745 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2748 dispc_ovl_set_row_inc(dispc, plane, row_inc); in dispc_ovl_setup_common()
2749 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); in dispc_ovl_setup_common()
2754 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); in dispc_ovl_setup_common()
2756 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); in dispc_ovl_setup_common()
2759 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, in dispc_ovl_setup_common()
2762 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); in dispc_ovl_setup_common()
2763 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); in dispc_ovl_setup_common()
2766 dispc_ovl_set_csc(dispc, plane, color_encoding, color_range); in dispc_ovl_setup_common()
2769 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, in dispc_ovl_setup_common()
2772 dispc_ovl_set_zorder(dispc, plane, caps, zorder); in dispc_ovl_setup_common()
2773 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); in dispc_ovl_setup_common()
2774 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); in dispc_ovl_setup_common()
2776 dispc_ovl_enable_replication(dispc, plane, caps, replication); in dispc_ovl_setup_common()
2781 int dispc_ovl_setup(struct dispc_device *dispc, in dispc_ovl_setup() argument
2788 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2797 dispc_ovl_set_channel_out(dispc, plane, channel); in dispc_ovl_setup()
2799 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2809 int dispc_wb_setup(struct dispc_device *dispc, in dispc_wb_setup() argument
2833 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2859 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_wb_setup()
2867 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_wb_setup()
2871 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); in dispc_wb_setup()
2887 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); in dispc_wb_setup()
2893 bool dispc_has_writeback(struct dispc_device *dispc) in dispc_has_writeback() argument
2895 return dispc->feat->has_writeback; in dispc_has_writeback()
2898 int dispc_ovl_enable(struct dispc_device *dispc, in dispc_ovl_enable() argument
2903 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); in dispc_ovl_enable()
2908 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, in dispc_lcd_enable_signal_polarity() argument
2911 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) in dispc_lcd_enable_signal_polarity()
2914 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2917 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) in dispc_lcd_enable_signal() argument
2919 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) in dispc_lcd_enable_signal()
2922 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2925 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) in dispc_pck_free_enable() argument
2927 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) in dispc_pck_free_enable()
2930 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2933 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, in dispc_mgr_enable_fifohandcheck() argument
2937 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); in dispc_mgr_enable_fifohandcheck()
2941 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, in dispc_mgr_set_lcd_type_tft() argument
2944 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); in dispc_mgr_set_lcd_type_tft()
2947 static void dispc_set_loadmode(struct dispc_device *dispc, in dispc_set_loadmode() argument
2950 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2954 static void dispc_mgr_set_default_color(struct dispc_device *dispc, in dispc_mgr_set_default_color() argument
2957 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); in dispc_mgr_set_default_color()
2960 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, in dispc_mgr_set_trans_key() argument
2965 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); in dispc_mgr_set_trans_key()
2967 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); in dispc_mgr_set_trans_key()
2970 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, in dispc_mgr_enable_trans_key() argument
2973 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); in dispc_mgr_enable_trans_key()
2976 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, in dispc_mgr_enable_alpha_fixed_zorder() argument
2980 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) in dispc_mgr_enable_alpha_fixed_zorder()
2984 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2986 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
2989 void dispc_mgr_setup(struct dispc_device *dispc, in dispc_mgr_setup() argument
2993 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
2994 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
2996 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
2997 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, in dispc_mgr_setup()
2999 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_mgr_setup()
3000 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
3001 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
3005 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, in dispc_mgr_set_tft_data_lines() argument
3029 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); in dispc_mgr_set_tft_data_lines()
3032 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, in dispc_mgr_set_io_pad_mode() argument
3056 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
3059 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3062 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, in dispc_mgr_enable_stallmode() argument
3065 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); in dispc_mgr_enable_stallmode()
3068 void dispc_mgr_set_lcd_config(struct dispc_device *dispc, in dispc_mgr_set_lcd_config() argument
3072 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3074 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3075 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3077 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3079 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3081 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3083 dispc_mgr_set_lcd_type_tft(dispc, channel); in dispc_mgr_set_lcd_config()
3086 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, in _dispc_mgr_size_ok() argument
3089 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3090 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3093 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, in _dispc_lcd_timings_ok() argument
3097 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3098 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3099 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3100 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3101 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3102 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3107 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, in _dispc_mgr_pclk_ok() argument
3112 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3114 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3117 int dispc_mgr_check_timings(struct dispc_device *dispc, in dispc_mgr_check_timings() argument
3121 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3124 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3132 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3142 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, in _dispc_mgr_set_lcd_timings() argument
3149 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3150 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3151 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3152 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3153 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3154 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3156 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); in _dispc_mgr_set_lcd_timings()
3157 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); in _dispc_mgr_set_lcd_timings()
3174 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3177 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); in _dispc_mgr_set_lcd_timings()
3179 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3194 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3210 void dispc_mgr_set_timings(struct dispc_device *dispc, in dispc_mgr_set_timings() argument
3220 if (dispc_mgr_check_timings(dispc, channel, &t)) { in dispc_mgr_set_timings()
3226 _dispc_mgr_set_lcd_timings(dispc, channel, &t); in dispc_mgr_set_timings()
3250 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3251 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3256 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); in dispc_mgr_set_timings()
3259 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_set_lcd_divisor() argument
3266 dispc_write_reg(dispc, DISPC_DIVISORo(channel), in dispc_mgr_set_lcd_divisor()
3269 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && in dispc_mgr_set_lcd_divisor()
3271 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3274 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_get_lcd_divisor() argument
3279 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_get_lcd_divisor()
3284 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) in dispc_fclk_rate() argument
3289 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3292 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3297 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3306 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, in dispc_mgr_lclk_rate() argument
3315 return dispc_fclk_rate(dispc); in dispc_mgr_lclk_rate()
3317 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3320 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3325 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3331 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3336 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, in dispc_mgr_pclk_rate() argument
3345 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_pclk_rate()
3349 r = dispc_mgr_lclk_rate(dispc, channel); in dispc_mgr_pclk_rate()
3353 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3357 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) in dispc_set_tv_pclk() argument
3359 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3362 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) in dispc_core_clk_rate() argument
3364 return dispc->core_clk_rate; in dispc_core_clk_rate()
3367 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, in dispc_plane_pclk_rate() argument
3375 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_pclk_rate()
3377 return dispc_mgr_pclk_rate(dispc, channel); in dispc_plane_pclk_rate()
3380 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, in dispc_plane_lclk_rate() argument
3388 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_lclk_rate()
3390 return dispc_mgr_lclk_rate(dispc, channel); in dispc_plane_lclk_rate()
3393 static void dispc_dump_clocks_channel(struct dispc_device *dispc, in dispc_dump_clocks_channel() argument
3402 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3407 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); in dispc_dump_clocks_channel()
3410 dispc_mgr_lclk_rate(dispc, channel), lcd); in dispc_dump_clocks_channel()
3412 dispc_mgr_pclk_rate(dispc, channel), pcd); in dispc_dump_clocks_channel()
3415 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) in dispc_dump_clocks() argument
3421 if (dispc_runtime_get(dispc)) in dispc_dump_clocks()
3426 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3430 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3432 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in dispc_dump_clocks()
3434 l = dispc_read_reg(dispc, DISPC_DIVISOR); in dispc_dump_clocks()
3438 (dispc_fclk_rate(dispc)/lcd), lcd); in dispc_dump_clocks()
3441 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); in dispc_dump_clocks()
3443 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_dump_clocks()
3444 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); in dispc_dump_clocks()
3445 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_dump_clocks()
3446 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); in dispc_dump_clocks()
3448 dispc_runtime_put(dispc); in dispc_dump_clocks()
3453 struct dispc_device *dispc = s->private; in dispc_dump_regs() local
3470 #define DUMPREG(dispc, r) \ in dispc_dump_regs() argument
3471 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3473 if (dispc_runtime_get(dispc)) in dispc_dump_regs()
3477 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3478 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3479 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3480 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3481 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3482 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3483 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3484 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3485 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
3486 DUMPREG(dispc, DISPC_LINE_NUMBER); in dispc_dump_regs()
3487 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_dump_regs()
3488 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_dump_regs()
3489 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); in dispc_dump_regs()
3490 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_dump_regs()
3491 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
3492 DUMPREG(dispc, DISPC_CONFIG2); in dispc_dump_regs()
3494 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_dump_regs()
3495 DUMPREG(dispc, DISPC_CONTROL3); in dispc_dump_regs()
3496 DUMPREG(dispc, DISPC_CONFIG3); in dispc_dump_regs()
3498 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3499 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); in dispc_dump_regs()
3504 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ in dispc_dump_regs() argument
3506 dispc_read_reg(dispc, DISPC_REG(i, r))) in dispc_dump_regs()
3511 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_dump_regs()
3512 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); in dispc_dump_regs()
3513 DUMPREG(dispc, i, DISPC_TRANS_COLOR); in dispc_dump_regs()
3514 DUMPREG(dispc, i, DISPC_SIZE_MGR); in dispc_dump_regs()
3519 DUMPREG(dispc, i, DISPC_TIMING_H); in dispc_dump_regs()
3520 DUMPREG(dispc, i, DISPC_TIMING_V); in dispc_dump_regs()
3521 DUMPREG(dispc, i, DISPC_POL_FREQ); in dispc_dump_regs()
3522 DUMPREG(dispc, i, DISPC_DIVISORo); in dispc_dump_regs()
3524 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); in dispc_dump_regs()
3525 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); in dispc_dump_regs()
3526 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); in dispc_dump_regs()
3528 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_dump_regs()
3529 DUMPREG(dispc, i, DISPC_CPR_COEF_R); in dispc_dump_regs()
3530 DUMPREG(dispc, i, DISPC_CPR_COEF_G); in dispc_dump_regs()
3531 DUMPREG(dispc, i, DISPC_CPR_COEF_B); in dispc_dump_regs()
3537 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3538 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3539 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3540 DUMPREG(dispc, i, DISPC_OVL_POSITION); in dispc_dump_regs()
3541 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3542 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3543 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3544 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3545 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3546 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3548 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_dump_regs()
3549 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); in dispc_dump_regs()
3550 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3551 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3554 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); in dispc_dump_regs()
3555 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); in dispc_dump_regs()
3559 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3560 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3561 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3562 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3563 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3564 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3565 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3566 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3567 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3568 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3570 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3571 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3574 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3576 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3577 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3578 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3579 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3580 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3581 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3582 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3583 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3585 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3586 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3588 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3589 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3590 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3591 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3592 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3593 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3594 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3595 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3596 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3597 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3599 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3600 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3607 #define DUMPREG(dispc, plane, name, i) \ in dispc_dump_regs() argument
3610 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) in dispc_dump_regs()
3615 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3617 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); in dispc_dump_regs()
3620 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); in dispc_dump_regs()
3623 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); in dispc_dump_regs()
3625 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_dump_regs()
3627 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); in dispc_dump_regs()
3630 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3632 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); in dispc_dump_regs()
3635 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); in dispc_dump_regs()
3638 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); in dispc_dump_regs()
3642 dispc_runtime_put(dispc); in dispc_dump_regs()
3651 int dispc_calc_clock_rates(struct dispc_device *dispc, in dispc_calc_clock_rates() argument
3666 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, in dispc_div_calc() argument
3684 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3687 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3710 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_div_calc()
3711 fck = dispc_core_clk_rate(dispc); in dispc_div_calc()
3726 void dispc_mgr_set_clock_div(struct dispc_device *dispc, in dispc_mgr_set_clock_div() argument
3733 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3737 int dispc_mgr_get_clock_div(struct dispc_device *dispc, in dispc_mgr_get_clock_div() argument
3743 fck = dispc_fclk_rate(dispc); in dispc_mgr_get_clock_div()
3745 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3746 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3754 u32 dispc_read_irqstatus(struct dispc_device *dispc) in dispc_read_irqstatus() argument
3756 return dispc_read_reg(dispc, DISPC_IRQSTATUS); in dispc_read_irqstatus()
3759 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) in dispc_clear_irqstatus() argument
3761 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); in dispc_clear_irqstatus()
3764 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) in dispc_write_irqenable() argument
3766 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3769 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_write_irqenable()
3771 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3774 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3777 void dispc_enable_sidle(struct dispc_device *dispc) in dispc_enable_sidle() argument
3780 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3783 void dispc_disable_sidle(struct dispc_device *dispc) in dispc_disable_sidle() argument
3785 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ in dispc_disable_sidle()
3788 u32 dispc_mgr_gamma_size(struct dispc_device *dispc, in dispc_mgr_gamma_size() argument
3793 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3799 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, in dispc_mgr_write_gamma_table() argument
3803 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3816 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3820 static void dispc_restore_gamma_tables(struct dispc_device *dispc) in dispc_restore_gamma_tables() argument
3824 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3827 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); in dispc_restore_gamma_tables()
3829 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); in dispc_restore_gamma_tables()
3831 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_gamma_tables()
3832 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); in dispc_restore_gamma_tables()
3834 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_gamma_tables()
3835 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); in dispc_restore_gamma_tables()
3843 void dispc_mgr_set_gamma(struct dispc_device *dispc, in dispc_mgr_set_gamma() argument
3849 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3855 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3887 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3888 dispc_mgr_write_gamma_table(dispc, channel); in dispc_mgr_set_gamma()
3891 static int dispc_init_gamma_tables(struct dispc_device *dispc) in dispc_init_gamma_tables() argument
3895 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3898 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3903 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_init_gamma_tables()
3907 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_init_gamma_tables()
3910 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3915 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3917 dispc_mgr_set_gamma(dispc, channel, NULL, 0); in dispc_init_gamma_tables()
3922 static void _omap_dispc_initial_config(struct dispc_device *dispc) in _omap_dispc_initial_config() argument
3927 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in _omap_dispc_initial_config()
3928 l = dispc_read_reg(dispc, DISPC_DIVISOR); in _omap_dispc_initial_config()
3932 dispc_write_reg(dispc, DISPC_DIVISOR, l); in _omap_dispc_initial_config()
3934 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3938 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3939 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3945 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || in _omap_dispc_initial_config()
3946 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3947 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
3949 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); in _omap_dispc_initial_config()
3951 dispc_init_fifos(dispc); in _omap_dispc_initial_config()
3953 dispc_configure_burst_sizes(dispc); in _omap_dispc_initial_config()
3955 dispc_ovl_enable_zorder_planes(dispc); in _omap_dispc_initial_config()
3957 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
3958 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); in _omap_dispc_initial_config()
3960 if (dispc_has_feature(dispc, FEAT_MFLAG)) in _omap_dispc_initial_config()
3961 dispc_init_mflag(dispc); in _omap_dispc_initial_config()
4491 struct dispc_device *dispc = arg; in dispc_irq_handler() local
4493 if (!dispc->is_enabled) in dispc_irq_handler()
4496 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4499 int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, in dispc_request_irq() argument
4504 if (dispc->user_handler != NULL) in dispc_request_irq()
4507 dispc->user_handler = handler; in dispc_request_irq()
4508 dispc->user_data = dev_id; in dispc_request_irq()
4513 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4514 IRQF_SHARED, "OMAP DISPC", dispc); in dispc_request_irq()
4516 dispc->user_handler = NULL; in dispc_request_irq()
4517 dispc->user_data = NULL; in dispc_request_irq()
4523 void dispc_free_irq(struct dispc_device *dispc, void *dev_id) in dispc_free_irq() argument
4525 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4527 dispc->user_handler = NULL; in dispc_free_irq()
4528 dispc->user_data = NULL; in dispc_free_irq()
4531 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) in dispc_get_memory_bandwidth_limit() argument
4536 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4613 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) in dispc_errata_i734_wa_init() argument
4615 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4621 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4624 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4632 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) in dispc_errata_i734_wa_fini() argument
4634 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4637 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4641 static void dispc_errata_i734_wa(struct dispc_device *dispc) in dispc_errata_i734_wa() argument
4643 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, in dispc_errata_i734_wa()
4650 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4653 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4660 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); in dispc_errata_i734_wa()
4663 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, in dispc_errata_i734_wa()
4665 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); in dispc_errata_i734_wa()
4668 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); in dispc_errata_i734_wa()
4669 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4671 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); in dispc_errata_i734_wa()
4672 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); in dispc_errata_i734_wa()
4674 dispc_clear_irqstatus(dispc, framedone_irq); in dispc_errata_i734_wa()
4677 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); in dispc_errata_i734_wa()
4678 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); in dispc_errata_i734_wa()
4685 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { in dispc_errata_i734_wa()
4687 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4692 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); in dispc_errata_i734_wa()
4695 dispc_clear_irqstatus(dispc, 0xffffffff); in dispc_errata_i734_wa()
4698 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); in dispc_errata_i734_wa()
4725 struct dispc_device *dispc; in dispc_bind() local
4731 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind()
4732 if (!dispc) in dispc_bind()
4735 dispc->pdev = pdev; in dispc_bind()
4736 platform_set_drvdata(pdev, dispc); in dispc_bind()
4737 dispc->dss = dss; in dispc_bind()
4745 dispc->feat = soc->data; in dispc_bind()
4747 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; in dispc_bind()
4749 r = dispc_errata_i734_wa_init(dispc); in dispc_bind()
4753 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); in dispc_bind()
4754 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); in dispc_bind()
4755 if (IS_ERR(dispc->base)) { in dispc_bind()
4756 r = PTR_ERR(dispc->base); in dispc_bind()
4760 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4761 if (dispc->irq < 0) { in dispc_bind()
4768 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4769 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4771 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4776 &dispc->syscon_pol_offset)) { in dispc_bind()
4783 r = dispc_init_gamma_tables(dispc); in dispc_bind()
4789 r = dispc_runtime_get(dispc); in dispc_bind()
4793 _omap_dispc_initial_config(dispc); in dispc_bind()
4795 rev = dispc_read_reg(dispc, DISPC_REVISION); in dispc_bind()
4799 dispc_runtime_put(dispc); in dispc_bind()
4801 dss->dispc = dispc; in dispc_bind()
4803 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4804 dispc); in dispc_bind()
4811 kfree(dispc); in dispc_bind()
4817 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_unbind() local
4818 struct dss_device *dss = dispc->dss; in dispc_unbind()
4820 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4822 dss->dispc = NULL; in dispc_unbind()
4826 dispc_errata_i734_wa_fini(dispc); in dispc_unbind()
4828 kfree(dispc); in dispc_unbind()
4849 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_suspend() local
4851 dispc->is_enabled = false; in dispc_runtime_suspend()
4855 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4857 dispc_save_context(dispc); in dispc_runtime_suspend()
4864 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_resume() local
4872 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
4873 _omap_dispc_initial_config(dispc); in dispc_runtime_resume()
4875 dispc_errata_i734_wa(dispc); in dispc_runtime_resume()
4877 dispc_restore_context(dispc); in dispc_runtime_resume()
4879 dispc_restore_gamma_tables(dispc); in dispc_runtime_resume()
4882 dispc->is_enabled = true; in dispc_runtime_resume()