576 				WREG32_SMC(config_regs->offset, data);  in ci_program_pt_config_registers()
866 	WREG32_SMC(CG_THERMAL_INT, tmp);  in ci_thermal_set_temperature_range()
873 	WREG32_SMC(CG_THERMAL_CTRL, tmp);  in ci_thermal_set_temperature_range()
890 		WREG32_SMC(CG_THERMAL_INT, thermal_int);  in ci_thermal_enable_alert()
899 		WREG32_SMC(CG_THERMAL_INT, thermal_int);  in ci_thermal_enable_alert()
926 	WREG32_SMC(CG_FDO_CTRL2, tmp);  in ci_fan_ctrl_set_static_mode()
930 	WREG32_SMC(CG_FDO_CTRL2, tmp);  in ci_fan_ctrl_set_static_mode()
1104 	WREG32_SMC(CG_FDO_CTRL0, tmp);  in ci_fan_ctrl_set_fan_speed_percent()
1181 	WREG32_SMC(CG_TACH_CTRL, tmp);
1197 		WREG32_SMC(CG_FDO_CTRL2, tmp);  in ci_fan_ctrl_set_default_mode()
1201 		WREG32_SMC(CG_FDO_CTRL2, tmp);  in ci_fan_ctrl_set_default_mode()
1221 		WREG32_SMC(CG_TACH_CTRL, tmp);  in ci_thermal_initialize()
1226 	WREG32_SMC(CG_FDO_CTRL2, tmp);  in ci_thermal_initialize()
1385 		WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_set_dpm_event_sources()
1389 		WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_set_dpm_event_sources()
1463 			WREG32_SMC(LCAC_MC0_CNTL, 0x05);  in ci_enable_sclk_mclk_dpm()
1464 			WREG32_SMC(LCAC_MC1_CNTL, 0x05);  in ci_enable_sclk_mclk_dpm()
1465 			WREG32_SMC(LCAC_CPL_CNTL, 0x100005);  in ci_enable_sclk_mclk_dpm()
1469 			WREG32_SMC(LCAC_MC0_CNTL, 0x400005);  in ci_enable_sclk_mclk_dpm()
1470 			WREG32_SMC(LCAC_MC1_CNTL, 0x400005);  in ci_enable_sclk_mclk_dpm()
1471 			WREG32_SMC(LCAC_CPL_CNTL, 0x500005);  in ci_enable_sclk_mclk_dpm()
1499 	WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_start_dpm()
1503 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);  in ci_start_dpm()
1560 	WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_stop_dpm()
1564 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);  in ci_stop_dpm()
1591 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);  in ci_enable_sclk_control()
1877 	WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_enable_thermal_protection()
1886 	WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_enable_acpi_power_management()
1963 	WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);  in ci_program_display_gap()
1974 	WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);  in ci_program_display_gap()
1992 			WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_enable_spread_spectrum()
1997 		WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);  in ci_enable_spread_spectrum()
2001 		WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_enable_spread_spectrum()
2007 	WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));  in ci_program_sstp()
2018 	WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);  in ci_enable_display_gap()
2027 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);  in ci_program_vc()
2029 	WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);  in ci_program_vc()
2030 	WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);  in ci_program_vc()
2031 	WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);  in ci_program_vc()
2032 	WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);  in ci_program_vc()
2033 	WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);  in ci_program_vc()
2034 	WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);  in ci_program_vc()
2035 	WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);  in ci_program_vc()
2036 	WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);  in ci_program_vc()
2045 	WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);  in ci_clear_vc()
2047 	WREG32_SMC(CG_FTV_0, 0);  in ci_clear_vc()
2048 	WREG32_SMC(CG_FTV_1, 0);  in ci_clear_vc()
2049 	WREG32_SMC(CG_FTV_2, 0);  in ci_clear_vc()
2050 	WREG32_SMC(CG_FTV_3, 0);  in ci_clear_vc()
2051 	WREG32_SMC(CG_FTV_4, 0);  in ci_clear_vc()
2052 	WREG32_SMC(CG_FTV_5, 0);  in ci_clear_vc()
2053 	WREG32_SMC(CG_FTV_6, 0);  in ci_clear_vc()
2054 	WREG32_SMC(CG_FTV_7, 0);  in ci_clear_vc()
2066 	WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);  in ci_upload_firmware()
3549 		WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);  in ci_init_smc_table()
4057 		WREG32_SMC(DPM_TABLE_475, tmp);  in ci_update_uvd_dpm()
4095 			WREG32_SMC(DPM_TABLE_475, tmp);  in ci_update_vce_dpm()
4125 		WREG32_SMC(DPM_TABLE_475, tmp);
4758 	WREG32_SMC(GENERAL_PWRMGT, tmp);  in ci_enable_voltage_control()
5848 		WREG32_SMC(CNB_PWRMGT_CNTL, tmp);  in ci_dpm_init()