Lines Matching refs:track
301 static void r600_cs_track_init(struct r600_cs_track *track) in r600_cs_track_init() argument
306 track->sq_config = DX9_CONSTS; in r600_cs_track_init()
308 track->cb_color_base_last[i] = 0; in r600_cs_track_init()
309 track->cb_color_size[i] = 0; in r600_cs_track_init()
310 track->cb_color_size_idx[i] = 0; in r600_cs_track_init()
311 track->cb_color_info[i] = 0; in r600_cs_track_init()
312 track->cb_color_view[i] = 0xFFFFFFFF; in r600_cs_track_init()
313 track->cb_color_bo[i] = NULL; in r600_cs_track_init()
314 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
315 track->cb_color_bo_mc[i] = 0xFFFFFFFF; in r600_cs_track_init()
316 track->cb_color_frag_bo[i] = NULL; in r600_cs_track_init()
317 track->cb_color_frag_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
318 track->cb_color_tile_bo[i] = NULL; in r600_cs_track_init()
319 track->cb_color_tile_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
320 track->cb_color_mask[i] = 0xFFFFFFFF; in r600_cs_track_init()
322 track->is_resolve = false; in r600_cs_track_init()
323 track->nsamples = 16; in r600_cs_track_init()
324 track->log_nsamples = 4; in r600_cs_track_init()
325 track->cb_target_mask = 0xFFFFFFFF; in r600_cs_track_init()
326 track->cb_shader_mask = 0xFFFFFFFF; in r600_cs_track_init()
327 track->cb_dirty = true; in r600_cs_track_init()
328 track->db_bo = NULL; in r600_cs_track_init()
329 track->db_bo_mc = 0xFFFFFFFF; in r600_cs_track_init()
331 track->db_depth_info = 7 | (1 << 25); in r600_cs_track_init()
332 track->db_depth_view = 0xFFFFC000; in r600_cs_track_init()
333 track->db_depth_size = 0xFFFFFFFF; in r600_cs_track_init()
334 track->db_depth_size_idx = 0; in r600_cs_track_init()
335 track->db_depth_control = 0xFFFFFFFF; in r600_cs_track_init()
336 track->db_dirty = true; in r600_cs_track_init()
337 track->htile_bo = NULL; in r600_cs_track_init()
338 track->htile_offset = 0xFFFFFFFF; in r600_cs_track_init()
339 track->htile_surface = 0; in r600_cs_track_init()
342 track->vgt_strmout_size[i] = 0; in r600_cs_track_init()
343 track->vgt_strmout_bo[i] = NULL; in r600_cs_track_init()
344 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
345 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; in r600_cs_track_init()
347 track->streamout_dirty = true; in r600_cs_track_init()
348 track->sx_misc_kill_all_prims = false; in r600_cs_track_init()
353 struct r600_cs_track *track = p->track; in r600_cs_track_validate_cb() local
362 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; in r600_cs_track_validate_cb()
364 format = G_0280A0_FORMAT(track->cb_color_info[i]); in r600_cs_track_validate_cb()
368 i, track->cb_color_info[i]); in r600_cs_track_validate_cb()
372 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; in r600_cs_track_validate_cb()
373 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; in r600_cs_track_validate_cb()
378 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); in r600_cs_track_validate_cb()
380 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; in r600_cs_track_validate_cb()
382 array_check.group_size = track->group_size; in r600_cs_track_validate_cb()
383 array_check.nbanks = track->nbanks; in r600_cs_track_validate_cb()
384 array_check.npipes = track->npipes; in r600_cs_track_validate_cb()
390 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, in r600_cs_track_validate_cb()
391 track->cb_color_info[i]); in r600_cs_track_validate_cb()
408 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, in r600_cs_track_validate_cb()
409 track->cb_color_info[i]); in r600_cs_track_validate_cb()
436 tmp += track->cb_color_view[i] & 0xFF; in r600_cs_track_validate_cb()
440 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; in r600_cs_track_validate_cb()
443 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { in r600_cs_track_validate_cb()
454 track->cb_color_bo_offset[i], tmp, in r600_cs_track_validate_cb()
455 radeon_bo_size(track->cb_color_bo[i]), in r600_cs_track_validate_cb()
468 ib[track->cb_color_size_idx[i]] = tmp; in r600_cs_track_validate_cb()
471 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { in r600_cs_track_validate_cb()
475 if (track->nsamples > 1) { in r600_cs_track_validate_cb()
476 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); in r600_cs_track_validate_cb()
479 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); in r600_cs_track_validate_cb()
481 if (bytes + track->cb_color_frag_offset[i] > in r600_cs_track_validate_cb()
482 radeon_bo_size(track->cb_color_frag_bo[i])) { in r600_cs_track_validate_cb()
486 track->cb_color_frag_offset[i], in r600_cs_track_validate_cb()
487 radeon_bo_size(track->cb_color_frag_bo[i])); in r600_cs_track_validate_cb()
494 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); in r600_cs_track_validate_cb()
499 if (bytes + track->cb_color_tile_offset[i] > in r600_cs_track_validate_cb()
500 radeon_bo_size(track->cb_color_tile_bo[i])) { in r600_cs_track_validate_cb()
504 track->cb_color_tile_offset[i], in r600_cs_track_validate_cb()
505 radeon_bo_size(track->cb_color_tile_bo[i])); in r600_cs_track_validate_cb()
519 struct r600_cs_track *track = p->track; in r600_cs_track_validate_db() local
530 if (track->db_bo == NULL) { in r600_cs_track_validate_db()
534 switch (G_028010_FORMAT(track->db_depth_info)) { in r600_cs_track_validate_db()
549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); in r600_cs_track_validate_db()
552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { in r600_cs_track_validate_db()
553 if (!track->db_depth_size_idx) { in r600_cs_track_validate_db()
557 tmp = radeon_bo_size(track->db_bo) - track->db_offset; in r600_cs_track_validate_db()
561 track->db_depth_size, bpe, track->db_offset, in r600_cs_track_validate_db()
562 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); in r600_cs_track_validate_db()
568 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; in r600_cs_track_validate_db()
569 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; in r600_cs_track_validate_db()
574 base_offset = track->db_bo_mc + track->db_offset; in r600_cs_track_validate_db()
575 array_mode = G_028010_ARRAY_MODE(track->db_depth_info); in r600_cs_track_validate_db()
577 array_check.group_size = track->group_size; in r600_cs_track_validate_db()
578 array_check.nbanks = track->nbanks; in r600_cs_track_validate_db()
579 array_check.npipes = track->npipes; in r600_cs_track_validate_db()
580 array_check.nsamples = track->nsamples; in r600_cs_track_validate_db()
585 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
586 track->db_depth_info); in r600_cs_track_validate_db()
598 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
599 track->db_depth_info); in r600_cs_track_validate_db()
619 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; in r600_cs_track_validate_db()
620 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; in r600_cs_track_validate_db()
621 tmp = ntiles * bpe * 64 * nviews * track->nsamples; in r600_cs_track_validate_db()
622 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { in r600_cs_track_validate_db()
625 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, in r600_cs_track_validate_db()
626 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
632 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { in r600_cs_track_validate_db()
636 if (track->htile_bo == NULL) { in r600_cs_track_validate_db()
638 __func__, __LINE__, track->db_depth_info); in r600_cs_track_validate_db()
641 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { in r600_cs_track_validate_db()
643 __func__, __LINE__, track->db_depth_size); in r600_cs_track_validate_db()
649 if (G_028D24_LINEAR(track->htile_surface)) { in r600_cs_track_validate_db()
653 nby = round_up(nby, track->npipes * 8); in r600_cs_track_validate_db()
659 switch (track->npipes) { in r600_cs_track_validate_db()
682 __func__, __LINE__, track->npipes); in r600_cs_track_validate_db()
690 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in r600_cs_track_validate_db()
691 size += track->htile_offset; in r600_cs_track_validate_db()
693 if (size > radeon_bo_size(track->htile_bo)) { in r600_cs_track_validate_db()
695 __func__, __LINE__, radeon_bo_size(track->htile_bo), in r600_cs_track_validate_db()
701 track->db_dirty = false; in r600_cs_track_validate_db()
707 struct r600_cs_track *track = p->track; in r600_cs_track_check() local
716 if (track->streamout_dirty && track->vgt_strmout_en) { in r600_cs_track_check()
718 if (track->vgt_strmout_buffer_en & (1 << i)) { in r600_cs_track_check()
719 if (track->vgt_strmout_bo[i]) { in r600_cs_track_check()
720 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in r600_cs_track_check()
721 (u64)track->vgt_strmout_size[i]; in r600_cs_track_check()
722 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in r600_cs_track_check()
725 radeon_bo_size(track->vgt_strmout_bo[i])); in r600_cs_track_check()
734 track->streamout_dirty = false; in r600_cs_track_check()
737 if (track->sx_misc_kill_all_prims) in r600_cs_track_check()
743 if (track->cb_dirty) { in r600_cs_track_check()
744 tmp = track->cb_target_mask; in r600_cs_track_check()
747 if (track->is_resolve) { in r600_cs_track_check()
752 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); in r600_cs_track_check()
757 if (track->cb_color_bo[i] == NULL) { in r600_cs_track_check()
759 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in r600_cs_track_check()
768 track->cb_dirty = false; in r600_cs_track_check()
772 if (track->db_dirty && in r600_cs_track_check()
773 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && in r600_cs_track_check()
774 (G_028800_STENCIL_ENABLE(track->db_depth_control) || in r600_cs_track_check()
775 G_028800_Z_ENABLE(track->db_depth_control))) { in r600_cs_track_check()
970 struct r600_cs_track *track = (struct r600_cs_track *)p->track; in r600_cs_check_reg() local
1025 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1028 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1029 track->db_dirty = true; in r600_cs_check_reg()
1040 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1042 track->db_depth_info &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1045 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1048 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1051 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1053 track->db_dirty = true; in r600_cs_check_reg()
1056 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1057 track->db_dirty = true; in r600_cs_check_reg()
1060 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1061 track->db_depth_size_idx = idx; in r600_cs_check_reg()
1062 track->db_dirty = true; in r600_cs_check_reg()
1065 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1066 track->streamout_dirty = true; in r600_cs_check_reg()
1069 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1070 track->streamout_dirty = true; in r600_cs_check_reg()
1083 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1085 track->vgt_strmout_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1086 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1087 track->streamout_dirty = true; in r600_cs_check_reg()
1095 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1096 track->streamout_dirty = true; in r600_cs_check_reg()
1108 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1109 track->cb_dirty = true; in r600_cs_check_reg()
1112 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1116 track->log_nsamples = tmp; in r600_cs_check_reg()
1117 track->nsamples = 1 << tmp; in r600_cs_check_reg()
1118 track->cb_dirty = true; in r600_cs_check_reg()
1122 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; in r600_cs_check_reg()
1123 track->cb_dirty = true; in r600_cs_check_reg()
1141 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1144 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1147 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1151 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1153 track->cb_dirty = true; in r600_cs_check_reg()
1164 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1165 track->cb_dirty = true; in r600_cs_check_reg()
1176 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1177 track->cb_color_size_idx[tmp] = idx; in r600_cs_check_reg()
1178 track->cb_dirty = true; in r600_cs_check_reg()
1199 if (!track->cb_color_base_last[tmp]) { in r600_cs_check_reg()
1203 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; in r600_cs_check_reg()
1204 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()
1205 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1212 track->cb_color_frag_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1213 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1216 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1217 track->cb_dirty = true; in r600_cs_check_reg()
1230 if (!track->cb_color_base_last[tmp]) { in r600_cs_check_reg()
1234 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; in r600_cs_check_reg()
1235 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()
1236 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1243 track->cb_color_tile_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1244 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1247 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1248 track->cb_dirty = true; in r600_cs_check_reg()
1260 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1261 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1262 track->cb_dirty = true; in r600_cs_check_reg()
1280 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1282 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1283 track->cb_color_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1284 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1285 track->cb_dirty = true; in r600_cs_check_reg()
1294 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1296 track->db_bo = reloc->robj; in r600_cs_check_reg()
1297 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
1298 track->db_dirty = true; in r600_cs_check_reg()
1307 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1309 track->htile_bo = reloc->robj; in r600_cs_check_reg()
1310 track->db_dirty = true; in r600_cs_check_reg()
1313 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1316 track->db_dirty = true; in r600_cs_check_reg()
1389 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1478 struct r600_cs_track *track = p->track; in r600_check_texture_resource() local
1518 array_check.group_size = track->group_size; in r600_check_texture_resource()
1519 array_check.nbanks = track->nbanks; in r600_check_texture_resource()
1520 array_check.npipes = track->npipes; in r600_check_texture_resource()
1632 struct r600_cs_track *track; in r600_packet3_check() local
1640 track = (struct r600_cs_track *)p->track; in r600_packet3_check()
2026 if (track->sq_config & DX9_CONSTS) { in r600_packet3_check()
2104 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { in r600_packet3_check()
2110 if (offset != track->vgt_strmout_bo_offset[idx_value]) { in r600_packet3_check()
2112 offset, track->vgt_strmout_bo_offset[idx_value]); in r600_packet3_check()
2273 struct r600_cs_track *track; in r600_cs_parse() local
2276 if (p->track == NULL) { in r600_cs_parse()
2278 track = kzalloc(sizeof(*track), GFP_KERNEL); in r600_cs_parse()
2279 if (track == NULL) in r600_cs_parse()
2281 r600_cs_track_init(track); in r600_cs_parse()
2283 track->npipes = p->rdev->config.r600.tiling_npipes; in r600_cs_parse()
2284 track->nbanks = p->rdev->config.r600.tiling_nbanks; in r600_cs_parse()
2285 track->group_size = p->rdev->config.r600.tiling_group_size; in r600_cs_parse()
2287 track->npipes = p->rdev->config.rv770.tiling_npipes; in r600_cs_parse()
2288 track->nbanks = p->rdev->config.rv770.tiling_nbanks; in r600_cs_parse()
2289 track->group_size = p->rdev->config.rv770.tiling_group_size; in r600_cs_parse()
2291 p->track = track; in r600_cs_parse()
2296 kfree(p->track); in r600_cs_parse()
2297 p->track = NULL; in r600_cs_parse()
2312 kfree(p->track); in r600_cs_parse()
2313 p->track = NULL; in r600_cs_parse()
2317 kfree(p->track); in r600_cs_parse()
2318 p->track = NULL; in r600_cs_parse()
2328 kfree(p->track); in r600_cs_parse()
2329 p->track = NULL; in r600_cs_parse()