Lines Matching refs:VC5_PHY_REG

147 #define VC5_PHY_REG(reg, offset)	_VC4_REG(VC5_PHY, reg, offset)  macro
249 	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
250 	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
251 	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
252 	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
253 	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
254 	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
255 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
256 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
257 	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
258 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
259 	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
260 	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
261 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
262 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
263 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
330 	VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
331 	VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
332 	VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
333 	VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
334 	VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
335 	VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
336 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
337 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
338 	VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
339 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
340 	VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
341 	VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
342 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
343 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
344 	VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),