Lines Matching refs:ipu
29 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) in ipu_cm_read() argument
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
34 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) in ipu_cm_write() argument
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
39 int ipu_get_num(struct ipu_soc *ipu) in ipu_get_num() argument
41 return ipu->id; in ipu_get_num()
45 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) in ipu_srm_dp_update() argument
49 val = ipu_cm_read(ipu, IPU_SRM_PRI2); in ipu_srm_dp_update()
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2); in ipu_srm_dp_update()
200 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
204 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
209 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
211 list_for_each_entry(channel, &ipu->channels, list) { in ipu_idmac_get()
225 channel->ipu = ipu; in ipu_idmac_get()
226 list_add(&channel->list, &ipu->channels); in ipu_idmac_get()
229 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
237 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put() local
239 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
241 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
246 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
265 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer() local
268 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); in __ipu_idmac_reset_current_buffer()
274 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer() local
278 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
280 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
285 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
289 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
319 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable() local
347 if (bursts && ipu->ipu_type != IPUV3H) in ipu_idmac_lock_enable()
357 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
359 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
362 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
364 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
370 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) in ipu_module_enable() argument
375 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
377 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_enable()
384 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_enable()
386 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_enable()
388 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_enable()
390 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
396 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) in ipu_module_disable() argument
401 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
403 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_disable()
405 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_disable()
407 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_disable()
414 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_disable()
416 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
424 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer() local
427 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; in ipu_idmac_get_current_buffer()
433 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready() local
437 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
440 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
443 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
446 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
449 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
457 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer() local
461 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
465 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_select_buffer()
467 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_select_buffer()
469 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
475 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer() local
479 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
481 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ in ipu_idmac_clear_buffer()
484 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_clear_buffer()
487 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_clear_buffer()
490 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); in ipu_idmac_clear_buffer()
495 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_clear_buffer()
497 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
503 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel() local
507 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
509 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
511 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
513 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
519 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) in ipu_idmac_channel_busy() argument
521 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); in ipu_idmac_channel_busy()
527 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy() local
531 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
544 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel() local
548 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
551 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
553 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
558 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ in ipu_idmac_disable_channel()
560 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
562 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
566 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
568 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
572 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_disable_channel()
575 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
577 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
579 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
593 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark() local
597 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
599 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
604 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
606 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
610 static int ipu_memory_reset(struct ipu_soc *ipu) in ipu_memory_reset() argument
614 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); in ipu_memory_reset()
617 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { in ipu_memory_reset()
630 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) in ipu_set_csi_src_mux() argument
638 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
640 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_csi_src_mux()
645 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_csi_src_mux()
647 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
654 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) in ipu_set_ic_src_mux() argument
659 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
661 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_ic_src_mux()
672 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_ic_src_mux()
674 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
732 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_link() argument
742 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_link()
745 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_link()
748 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_link()
752 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_link()
755 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_link()
758 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_link()
766 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_unlink() argument
776 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_unlink()
779 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_unlink()
781 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_unlink()
785 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_unlink()
787 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_unlink()
790 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_unlink()
798 return ipu_fsu_link(src->ipu, src->num, sink->num); in ipu_idmac_link()
805 return ipu_fsu_unlink(src->ipu, src->num, sink->num); in ipu_idmac_unlink()
882 static int ipu_submodules_init(struct ipu_soc *ipu, in ipu_submodules_init() argument
889 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
891 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
897 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
904 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
911 ret = ipu_ic_init(ipu, dev, in ipu_submodules_init()
919 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, in ipu_submodules_init()
927 ret = ipu_image_convert_init(ipu, dev); in ipu_submodules_init()
933 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
940 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
947 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
954 ret = ipu_dmfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
961 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
967 ret = ipu_smfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
977 ipu_dp_exit(ipu); in ipu_submodules_init()
979 ipu_dmfc_exit(ipu); in ipu_submodules_init()
981 ipu_dc_exit(ipu); in ipu_submodules_init()
983 ipu_di_exit(ipu, 1); in ipu_submodules_init()
985 ipu_di_exit(ipu, 0); in ipu_submodules_init()
987 ipu_image_convert_exit(ipu); in ipu_submodules_init()
989 ipu_vdi_exit(ipu); in ipu_submodules_init()
991 ipu_ic_exit(ipu); in ipu_submodules_init()
993 ipu_csi_exit(ipu, 1); in ipu_submodules_init()
995 ipu_csi_exit(ipu, 0); in ipu_submodules_init()
997 ipu_cpmem_exit(ipu); in ipu_submodules_init()
1003 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) in ipu_irq_handle() argument
1010 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); in ipu_irq_handle()
1011 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); in ipu_irq_handle()
1014 generic_handle_domain_irq(ipu->domain, in ipu_irq_handle()
1021 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_irq_handler() local
1027 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_irq_handler()
1034 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_err_irq_handler() local
1040 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_err_irq_handler()
1045 int ipu_map_irq(struct ipu_soc *ipu, int irq) in ipu_map_irq() argument
1049 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
1051 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
1057 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, in ipu_idmac_channel_irq() argument
1060 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
1064 static void ipu_submodules_exit(struct ipu_soc *ipu) in ipu_submodules_exit() argument
1066 ipu_smfc_exit(ipu); in ipu_submodules_exit()
1067 ipu_dp_exit(ipu); in ipu_submodules_exit()
1068 ipu_dmfc_exit(ipu); in ipu_submodules_exit()
1069 ipu_dc_exit(ipu); in ipu_submodules_exit()
1070 ipu_di_exit(ipu, 1); in ipu_submodules_exit()
1071 ipu_di_exit(ipu, 0); in ipu_submodules_exit()
1072 ipu_image_convert_exit(ipu); in ipu_submodules_exit()
1073 ipu_vdi_exit(ipu); in ipu_submodules_exit()
1074 ipu_ic_exit(ipu); in ipu_submodules_exit()
1075 ipu_csi_exit(ipu, 1); in ipu_submodules_exit()
1076 ipu_csi_exit(ipu, 0); in ipu_submodules_exit()
1077 ipu_cpmem_exit(ipu); in ipu_submodules_exit()
1139 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) in ipu_add_client_devices() argument
1141 struct device *dev = ipu->dev; in ipu_add_client_devices()
1194 static int ipu_irq_init(struct ipu_soc *ipu) in ipu_irq_init() argument
1210 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1211 &irq_generic_chip_ops, ipu); in ipu_irq_init()
1212 if (!ipu->domain) { in ipu_irq_init()
1213 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1217 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1220 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1221 irq_domain_remove(ipu->domain); in ipu_irq_init()
1227 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); in ipu_irq_init()
1228 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); in ipu_irq_init()
1232 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1233 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1243 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); in ipu_irq_init()
1244 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, in ipu_irq_init()
1245 ipu); in ipu_irq_init()
1250 static void ipu_irq_exit(struct ipu_soc *ipu) in ipu_irq_exit() argument
1254 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); in ipu_irq_exit()
1255 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); in ipu_irq_exit()
1260 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1265 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1268 void ipu_dump(struct ipu_soc *ipu) in ipu_dump() argument
1272 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1273 ipu_cm_read(ipu, IPU_CONF)); in ipu_dump()
1274 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1275 ipu_idmac_read(ipu, IDMAC_CONF)); in ipu_dump()
1276 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1277 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); in ipu_dump()
1278 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1279 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); in ipu_dump()
1280 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1281 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); in ipu_dump()
1282 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1283 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); in ipu_dump()
1284 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1285 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); in ipu_dump()
1286 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1287 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); in ipu_dump()
1288 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1289 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1290 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1291 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
1292 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1293 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); in ipu_dump()
1294 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1295 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); in ipu_dump()
1296 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1297 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); in ipu_dump()
1298 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1299 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); in ipu_dump()
1301 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1302 ipu_cm_read(ipu, IPU_INT_CTRL(i))); in ipu_dump()
1309 struct ipu_soc *ipu; in ipu_probe() local
1331 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1332 if (!ipu) in ipu_probe()
1335 ipu->id = of_alias_get_id(np, "ipu"); in ipu_probe()
1336 if (ipu->id < 0) in ipu_probe()
1337 ipu->id = 0; in ipu_probe()
1341 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, in ipu_probe()
1342 "fsl,prg", ipu->id); in ipu_probe()
1343 if (!ipu->prg_priv) in ipu_probe()
1347 ipu->devtype = devtype; in ipu_probe()
1348 ipu->ipu_type = devtype->type; in ipu_probe()
1350 spin_lock_init(&ipu->lock); in ipu_probe()
1351 mutex_init(&ipu->channel_lock); in ipu_probe()
1352 INIT_LIST_HEAD(&ipu->channels); in ipu_probe()
1383 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1385 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1389 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1392 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1393 if (IS_ERR(ipu->clk)) { in ipu_probe()
1394 ret = PTR_ERR(ipu->clk); in ipu_probe()
1399 platform_set_drvdata(pdev, ipu); in ipu_probe()
1401 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1407 ipu->dev = &pdev->dev; in ipu_probe()
1408 ipu->irq_sync = irq_sync; in ipu_probe()
1409 ipu->irq_err = irq_err; in ipu_probe()
1416 ret = ipu_memory_reset(ipu); in ipu_probe()
1420 ret = ipu_irq_init(ipu); in ipu_probe()
1425 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), in ipu_probe()
1428 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1432 ret = ipu_add_client_devices(ipu, ipu_base); in ipu_probe()
1444 ipu_submodules_exit(ipu); in ipu_probe()
1446 ipu_irq_exit(ipu); in ipu_probe()
1449 clk_disable_unprepare(ipu->clk); in ipu_probe()
1455 struct ipu_soc *ipu = platform_get_drvdata(pdev); in ipu_remove() local
1458 ipu_submodules_exit(ipu); in ipu_remove()
1459 ipu_irq_exit(ipu); in ipu_remove()
1461 clk_disable_unprepare(ipu->clk); in ipu_remove()