Lines Matching refs:csa
70 struct csdev_access *csa; member
154 struct csdev_access *csa) in etm_detect_os_lock() argument
156 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); in etm_detect_os_lock()
162 struct csdev_access *csa, u32 val) in etm_write_os_lock() argument
168 etm4x_relaxed_write32(csa, val, TRCOSLAR); in etm_write_os_lock()
184 struct csdev_access *csa) in etm4_os_unlock_csa() argument
189 etm_write_os_lock(drvdata, csa, 0x0); in etm4_os_unlock_csa()
209 struct csdev_access *csa) in etm4_cs_lock() argument
212 if (csa->io_mem) in etm4_cs_lock()
213 CS_LOCK(csa->base); in etm4_cs_lock()
217 struct csdev_access *csa) in etm4_cs_unlock() argument
219 if (csa->io_mem) in etm4_cs_unlock()
220 CS_UNLOCK(csa->base); in etm4_cs_unlock()
378 struct csdev_access *csa = &csdev->access; in etm4_enable_hw() local
381 etm4_cs_unlock(drvdata, csa); in etm4_enable_hw()
391 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); in etm4_enable_hw()
399 if (!csa->io_mem) in etm4_enable_hw()
403 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) in etm4_enable_hw()
407 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); in etm4_enable_hw()
408 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); in etm4_enable_hw()
410 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); in etm4_enable_hw()
411 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); in etm4_enable_hw()
412 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); in etm4_enable_hw()
414 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); in etm4_enable_hw()
415 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); in etm4_enable_hw()
416 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); in etm4_enable_hw()
417 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); in etm4_enable_hw()
418 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); in etm4_enable_hw()
419 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); in etm4_enable_hw()
420 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); in etm4_enable_hw()
421 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); in etm4_enable_hw()
422 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); in etm4_enable_hw()
424 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); in etm4_enable_hw()
426 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); in etm4_enable_hw()
428 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); in etm4_enable_hw()
429 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); in etm4_enable_hw()
431 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); in etm4_enable_hw()
433 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); in etm4_enable_hw()
434 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); in etm4_enable_hw()
435 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); in etm4_enable_hw()
443 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); in etm4_enable_hw()
449 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); in etm4_enable_hw()
450 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); in etm4_enable_hw()
452 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); in etm4_enable_hw()
455 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); in etm4_enable_hw()
456 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); in etm4_enable_hw()
459 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); in etm4_enable_hw()
460 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); in etm4_enable_hw()
462 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); in etm4_enable_hw()
465 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); in etm4_enable_hw()
466 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); in etm4_enable_hw()
468 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); in etm4_enable_hw()
471 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_enable_hw()
477 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); in etm4_enable_hw()
485 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); in etm4_enable_hw()
489 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); in etm4_enable_hw()
492 if (!csa->io_mem) in etm4_enable_hw()
496 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) in etm4_enable_hw()
508 etm4_cs_lock(drvdata, csa); in etm4_enable_hw()
787 struct csdev_access *csa = &csdev->access; in etm4_disable_hw() local
790 etm4_cs_unlock(drvdata, csa); in etm4_disable_hw()
795 control = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_disable_hw()
797 etm4x_relaxed_write32(csa, control, TRCPDCR); in etm4_disable_hw()
800 control = etm4x_relaxed_read32(csa, TRCPRGCTLR); in etm4_disable_hw()
819 etm4x_relaxed_write32(csa, control, TRCPRGCTLR); in etm4_disable_hw()
822 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) in etm4_disable_hw()
828 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); in etm4_disable_hw()
834 etm4x_relaxed_read32(csa, TRCCNTVRn(i)); in etm4_disable_hw()
838 etm4_cs_lock(drvdata, csa); in etm4_disable_hw()
948 struct csdev_access *csa) in etm4_init_sysreg_access() argument
961 *csa = (struct csdev_access) { in etm4_init_sysreg_access()
968 *csa = (struct csdev_access) { in etm4_init_sysreg_access()
983 struct csdev_access *csa) in etm4_init_iomem_access() argument
1001 *csa = CSDEV_ACCESS_IOMEM(drvdata->base); in etm4_init_iomem_access()
1006 struct csdev_access *csa) in etm4_init_csdev_access() argument
1014 return etm4_init_iomem_access(drvdata, csa); in etm4_init_csdev_access()
1016 if (etm4_init_sysreg_access(drvdata, csa)) in etm4_init_csdev_access()
1056 struct csdev_access *csa; in etm4_init_arch_data() local
1060 csa = init_arg->csa; in etm4_init_arch_data()
1067 if (!etm4_init_csdev_access(drvdata, csa)) in etm4_init_arch_data()
1071 etm_detect_os_lock(drvdata, csa); in etm4_init_arch_data()
1074 etm4_os_unlock_csa(drvdata, csa); in etm4_init_arch_data()
1075 etm4_cs_unlock(drvdata, csa); in etm4_init_arch_data()
1080 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); in etm4_init_arch_data()
1122 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); in etm4_init_arch_data()
1130 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); in etm4_init_arch_data()
1181 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); in etm4_init_arch_data()
1207 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); in etm4_init_arch_data()
1214 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); in etm4_init_arch_data()
1236 etm4_cs_lock(drvdata, csa); in etm4_init_arch_data()
1594 struct csdev_access *csa; in __etm4_cpu_save() local
1601 csa = &csdev->access; in __etm4_cpu_save()
1610 etm4_cs_unlock(drvdata, csa); in __etm4_cpu_save()
1615 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { in __etm4_cpu_save()
1625 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); in __etm4_cpu_save()
1627 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); in __etm4_cpu_save()
1628 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); in __etm4_cpu_save()
1629 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); in __etm4_cpu_save()
1630 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); in __etm4_cpu_save()
1631 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); in __etm4_cpu_save()
1633 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); in __etm4_cpu_save()
1634 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); in __etm4_cpu_save()
1635 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); in __etm4_cpu_save()
1636 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); in __etm4_cpu_save()
1637 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); in __etm4_cpu_save()
1638 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); in __etm4_cpu_save()
1640 state->trcqctlr = etm4x_read32(csa, TRCQCTLR); in __etm4_cpu_save()
1642 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); in __etm4_cpu_save()
1643 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); in __etm4_cpu_save()
1644 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); in __etm4_cpu_save()
1646 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); in __etm4_cpu_save()
1649 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); in __etm4_cpu_save()
1652 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); in __etm4_cpu_save()
1653 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); in __etm4_cpu_save()
1655 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); in __etm4_cpu_save()
1658 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); in __etm4_cpu_save()
1659 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); in __etm4_cpu_save()
1660 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); in __etm4_cpu_save()
1665 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); in __etm4_cpu_save()
1668 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); in __etm4_cpu_save()
1669 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); in __etm4_cpu_save()
1671 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); in __etm4_cpu_save()
1675 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); in __etm4_cpu_save()
1676 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); in __etm4_cpu_save()
1687 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); in __etm4_cpu_save()
1690 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); in __etm4_cpu_save()
1692 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); in __etm4_cpu_save()
1694 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); in __etm4_cpu_save()
1696 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); in __etm4_cpu_save()
1698 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); in __etm4_cpu_save()
1700 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); in __etm4_cpu_save()
1703 state->trcpdcr = etm4x_read32(csa, TRCPDCR); in __etm4_cpu_save()
1706 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { in __etm4_cpu_save()
1722 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), in __etm4_cpu_save()
1725 etm4_cs_lock(drvdata, csa); in __etm4_cpu_save()
1749 struct csdev_access *csa = &drvdata->csdev->access; in __etm4_cpu_restore() local
1754 etm4_cs_unlock(drvdata, csa); in __etm4_cpu_restore()
1755 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); in __etm4_cpu_restore()
1757 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); in __etm4_cpu_restore()
1759 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); in __etm4_cpu_restore()
1760 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); in __etm4_cpu_restore()
1761 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); in __etm4_cpu_restore()
1762 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); in __etm4_cpu_restore()
1763 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); in __etm4_cpu_restore()
1765 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); in __etm4_cpu_restore()
1766 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); in __etm4_cpu_restore()
1767 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); in __etm4_cpu_restore()
1768 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); in __etm4_cpu_restore()
1769 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); in __etm4_cpu_restore()
1770 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); in __etm4_cpu_restore()
1772 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); in __etm4_cpu_restore()
1774 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); in __etm4_cpu_restore()
1775 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); in __etm4_cpu_restore()
1776 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); in __etm4_cpu_restore()
1778 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); in __etm4_cpu_restore()
1781 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); in __etm4_cpu_restore()
1784 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); in __etm4_cpu_restore()
1785 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); in __etm4_cpu_restore()
1787 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); in __etm4_cpu_restore()
1790 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); in __etm4_cpu_restore()
1791 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); in __etm4_cpu_restore()
1792 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); in __etm4_cpu_restore()
1797 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); in __etm4_cpu_restore()
1800 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); in __etm4_cpu_restore()
1801 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); in __etm4_cpu_restore()
1803 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); in __etm4_cpu_restore()
1807 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); in __etm4_cpu_restore()
1808 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); in __etm4_cpu_restore()
1812 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); in __etm4_cpu_restore()
1815 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); in __etm4_cpu_restore()
1817 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); in __etm4_cpu_restore()
1819 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); in __etm4_cpu_restore()
1821 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); in __etm4_cpu_restore()
1823 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); in __etm4_cpu_restore()
1825 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); in __etm4_cpu_restore()
1828 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); in __etm4_cpu_restore()
1841 etm4_cs_lock(drvdata, csa); in __etm4_cpu_restore()
1966 init_arg.csa = &desc.access; in etm4_probe()