Lines Matching refs:ctlr
111 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask) in hisi_i2c_enable_int() argument
113 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
116 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask) in hisi_i2c_disable_int() argument
118 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
121 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) in hisi_i2c_clear_int() argument
123 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
126 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) in hisi_i2c_handle_errors() argument
128 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
131 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_handle_errors()
134 dev_err(ctlr->dev, "rx fifo error read\n"); in hisi_i2c_handle_errors()
137 dev_err(ctlr->dev, "rx fifo error write\n"); in hisi_i2c_handle_errors()
140 dev_err(ctlr->dev, "tx fifo error read\n"); in hisi_i2c_handle_errors()
143 dev_err(ctlr->dev, "tx fifo error write\n"); in hisi_i2c_handle_errors()
147 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) in hisi_i2c_start_xfer() argument
149 struct i2c_msg *msg = ctlr->msgs; in hisi_i2c_start_xfer()
152 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
156 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
158 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
161 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
163 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
165 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
167 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
169 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_start_xfer()
170 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_start_xfer()
175 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr) in hisi_i2c_reset_xfer() argument
177 ctlr->msg_num = 0; in hisi_i2c_reset_xfer()
178 ctlr->xfer_err = 0; in hisi_i2c_reset_xfer()
179 ctlr->msg_tx_idx = 0; in hisi_i2c_reset_xfer()
180 ctlr->msg_rx_idx = 0; in hisi_i2c_reset_xfer()
181 ctlr->buf_tx_idx = 0; in hisi_i2c_reset_xfer()
182 ctlr->buf_rx_idx = 0; in hisi_i2c_reset_xfer()
194 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap); in hisi_i2c_master_xfer() local
198 hisi_i2c_reset_xfer(ctlr); in hisi_i2c_master_xfer()
199 ctlr->completion = &done; in hisi_i2c_master_xfer()
200 ctlr->msg_num = num; in hisi_i2c_master_xfer()
201 ctlr->msgs = msgs; in hisi_i2c_master_xfer()
203 hisi_i2c_start_xfer(ctlr); in hisi_i2c_master_xfer()
205 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { in hisi_i2c_master_xfer()
206 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_master_xfer()
207 synchronize_irq(ctlr->irq); in hisi_i2c_master_xfer()
208 i2c_recover_bus(&ctlr->adapter); in hisi_i2c_master_xfer()
209 dev_err(ctlr->dev, "bus transfer timeout\n"); in hisi_i2c_master_xfer()
213 if (ctlr->xfer_err) { in hisi_i2c_master_xfer()
214 hisi_i2c_handle_errors(ctlr); in hisi_i2c_master_xfer()
218 hisi_i2c_reset_xfer(ctlr); in hisi_i2c_master_xfer()
219 ctlr->completion = NULL; in hisi_i2c_master_xfer()
234 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) in hisi_i2c_read_rx_fifo() argument
239 while (ctlr->msg_rx_idx < ctlr->msg_num) { in hisi_i2c_read_rx_fifo()
240 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; in hisi_i2c_read_rx_fifo()
243 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
247 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
249 ctlr->buf_rx_idx < cur_msg->len) { in hisi_i2c_read_rx_fifo()
250 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); in hisi_i2c_read_rx_fifo()
251 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
254 if (ctlr->buf_rx_idx == cur_msg->len) { in hisi_i2c_read_rx_fifo()
255 ctlr->buf_rx_idx = 0; in hisi_i2c_read_rx_fifo()
256 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
266 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) in hisi_i2c_xfer_msg() argument
273 while (ctlr->msg_tx_idx < ctlr->msg_num) { in hisi_i2c_xfer_msg()
274 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; in hisi_i2c_xfer_msg()
275 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); in hisi_i2c_xfer_msg()
278 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) in hisi_i2c_xfer_msg()
281 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
283 ctlr->buf_tx_idx < cur_msg->len && max_write) { in hisi_i2c_xfer_msg()
292 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) in hisi_i2c_xfer_msg()
299 cur_msg->buf[ctlr->buf_tx_idx]); in hisi_i2c_xfer_msg()
301 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); in hisi_i2c_xfer_msg()
302 ctlr->buf_tx_idx++; in hisi_i2c_xfer_msg()
305 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
309 if (ctlr->buf_tx_idx == cur_msg->len) { in hisi_i2c_xfer_msg()
310 ctlr->buf_tx_idx = 0; in hisi_i2c_xfer_msg()
311 ctlr->msg_tx_idx++; in hisi_i2c_xfer_msg()
323 if (ctlr->msg_tx_idx == ctlr->msg_num) in hisi_i2c_xfer_msg()
324 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY); in hisi_i2c_xfer_msg()
329 struct hisi_i2c_controller *ctlr = context; in hisi_i2c_irq() local
337 if (!ctlr->completion) in hisi_i2c_irq()
340 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); in hisi_i2c_irq()
341 hisi_i2c_clear_int(ctlr, int_stat); in hisi_i2c_irq()
346 hisi_i2c_xfer_msg(ctlr); in hisi_i2c_irq()
349 ctlr->xfer_err = int_stat; in hisi_i2c_irq()
355 hisi_i2c_read_rx_fifo(ctlr); in hisi_i2c_irq()
363 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_irq()
364 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_irq()
365 complete(ctlr->completion); in hisi_i2c_irq()
377 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr, in hisi_i2c_set_scl() argument
385 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); in hisi_i2c_set_scl()
391 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
393 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
396 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; in hisi_i2c_set_scl()
399 writel(scl_hcnt, ctlr->iobase + reg_hcnt); in hisi_i2c_set_scl()
400 writel(scl_lcnt, ctlr->iobase + reg_lcnt); in hisi_i2c_set_scl()
403 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr) in hisi_i2c_configure_bus() argument
407 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); in hisi_i2c_configure_bus()
408 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
410 switch (ctlr->t.bus_freq_hz) { in hisi_i2c_configure_bus()
413 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT); in hisi_i2c_configure_bus()
417 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT); in hisi_i2c_configure_bus()
424 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in hisi_i2c_configure_bus()
425 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT); in hisi_i2c_configure_bus()
429 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
432 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
434 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
437 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); in hisi_i2c_configure_bus()
439 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); in hisi_i2c_configure_bus()
443 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_configure_bus()
448 struct hisi_i2c_controller *ctlr; in hisi_i2c_probe() local
455 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL); in hisi_i2c_probe()
456 if (!ctlr) in hisi_i2c_probe()
459 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); in hisi_i2c_probe()
460 if (IS_ERR(ctlr->iobase)) in hisi_i2c_probe()
461 return PTR_ERR(ctlr->iobase); in hisi_i2c_probe()
463 ctlr->irq = platform_get_irq(pdev, 0); in hisi_i2c_probe()
464 if (ctlr->irq < 0) in hisi_i2c_probe()
465 return ctlr->irq; in hisi_i2c_probe()
467 ctlr->dev = dev; in hisi_i2c_probe()
469 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); in hisi_i2c_probe()
471 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); in hisi_i2c_probe()
483 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()
485 hisi_i2c_configure_bus(ctlr); in hisi_i2c_probe()
487 adapter = &ctlr->adapter; in hisi_i2c_probe()
493 i2c_set_adapdata(adapter, ctlr); in hisi_i2c_probe()
499 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); in hisi_i2c_probe()
500 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", in hisi_i2c_probe()
501 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); in hisi_i2c_probe()