14 	struct arm_smmu_device smmu;  member
20 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)  in to_qcom_smmu()  argument
22 	return container_of(smmu, struct qcom_smmu, smmu);  in to_qcom_smmu()
25 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,  in qcom_adreno_smmu_write_sctlr()  argument
28 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_adreno_smmu_write_sctlr()
39 	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);  in qcom_adreno_smmu_write_sctlr()
47 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()  local
49 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
50 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
51 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
52 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
53 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
54 	info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
55 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
62 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
74 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()  local
80 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
125 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
155 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
161 					       struct arm_smmu_device *smmu,  in qcom_adreno_smmu_alloc_context_bank()  argument
175 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
178 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
181 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)  in qcom_adreno_can_do_ttbr1()  argument
183 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
207 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
249 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)  in qcom_smmu_cfg_probe()  argument
251 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_cfg_probe()
264 	if (smmu->num_mapping_groups > 128) {  in qcom_smmu_cfg_probe()
265 		dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n");  in qcom_smmu_cfg_probe()
266 		smmu->num_mapping_groups = 128;  in qcom_smmu_cfg_probe()
269 	last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
280 	arm_smmu_gr0_write(smmu, last_s2cr, reg);  in qcom_smmu_cfg_probe()
281 	reg = arm_smmu_gr0_read(smmu, last_s2cr);  in qcom_smmu_cfg_probe()
284 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
286 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
288 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
291 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
294 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
295 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_smmu_cfg_probe()
300 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
301 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
302 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
304 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
305 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
306 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
313 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)  in qcom_smmu_write_s2cr()  argument
315 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
316 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_write_s2cr()
345 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);  in qcom_smmu_write_s2cr()
356 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_reset()  argument
368 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
373 static int qcom_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_smmu500_reset()  argument
375 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu500_reset()
377 	arm_mmu500_reset(smmu);  in qcom_smmu500_reset()
380 		return qcom_sdm845_smmu500_reset(smmu);  in qcom_smmu500_reset()
401 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,  in qcom_smmu_create()  argument
410 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
414 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
416 	return &qsmmu->smmu;  in qcom_smmu_create()
441 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_smmu_impl_init()  argument
443 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
449 			return qcom_smmu_create(smmu, &qcom_smmu_impl);  in qcom_smmu_impl_init()
460 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);  in qcom_smmu_impl_init()
463 		return qcom_smmu_create(smmu, &qcom_smmu_impl);  in qcom_smmu_impl_init()
465 	return smmu;  in qcom_smmu_impl_init()