117 	struct intel_iommu *iommu;  in iommu_regset_show()  local
123 	for_each_active_iommu(iommu, drhd) {  in iommu_regset_show()
131 			   iommu->name, drhd->reg_base_addr);  in iommu_regset_show()
137 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in iommu_regset_show()
139 			value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);  in iommu_regset_show()
145 			value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);  in iommu_regset_show()
150 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in iommu_regset_show()
218 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)  in ctx_tbl_walk()  argument
240 		context = iommu_context_addr(iommu, bus, devfn, 0);  in ctx_tbl_walk()
249 		tbl_wlk.rt_entry = &iommu->root_entry[bus];  in ctx_tbl_walk()
253 		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {  in ctx_tbl_walk()
264 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)  in root_tbl_walk()  argument
269 	spin_lock_irqsave(&iommu->lock, flags);  in root_tbl_walk()
270 	seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,  in root_tbl_walk()
271 		   (u64)virt_to_phys(iommu->root_entry));  in root_tbl_walk()
280 		ctx_tbl_walk(m, iommu, bus);  in root_tbl_walk()
282 	spin_unlock_irqrestore(&iommu->lock, flags);  in root_tbl_walk()
288 	struct intel_iommu *iommu;  in dmar_translation_struct_show()  local
292 	for_each_active_iommu(iommu, drhd) {  in dmar_translation_struct_show()
293 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in dmar_translation_struct_show()
296 				   iommu->name);  in dmar_translation_struct_show()
299 		root_tbl_walk(m, iommu);  in dmar_translation_struct_show()
380 					  struct intel_iommu *iommu)  in invalidation_queue_entry_show()  argument
382 	int index, shift = qi_shift(iommu);  in invalidation_queue_entry_show()
386 	if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
393 		desc = iommu->qi->desc + offset;  in invalidation_queue_entry_show()
394 		if (ecap_smts(iommu->ecap))  in invalidation_queue_entry_show()
398 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
402 				   iommu->qi->desc_status[index]);  in invalidation_queue_entry_show()
409 	struct intel_iommu *iommu;  in invalidation_queue_show()  local
415 	for_each_active_iommu(iommu, drhd) {  in invalidation_queue_show()
416 		qi = iommu->qi;  in invalidation_queue_show()
417 		shift = qi_shift(iommu);  in invalidation_queue_show()
419 		if (!qi || !ecap_qis(iommu->ecap))  in invalidation_queue_show()
422 		seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);  in invalidation_queue_show()
427 			   dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,  in invalidation_queue_show()
428 			   dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);  in invalidation_queue_show()
429 		invalidation_queue_entry_show(m, iommu);  in invalidation_queue_show()
441 				    struct intel_iommu *iommu)  in ir_tbl_remap_entry_show()  argument
451 		ri_entry = &iommu->ir_table->base[idx];  in ir_tbl_remap_entry_show()
465 				     struct intel_iommu *iommu)  in ir_tbl_posted_entry_show()  argument
475 		pi_entry = &iommu->ir_table->base[idx];  in ir_tbl_posted_entry_show()
497 	struct intel_iommu *iommu;  in ir_translation_struct_show()  local
502 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
503 		if (!ecap_ir_support(iommu->ecap))  in ir_translation_struct_show()
507 			   iommu->name);  in ir_translation_struct_show()
509 		sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);  in ir_translation_struct_show()
510 		if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {  in ir_translation_struct_show()
511 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
513 			ir_tbl_remap_entry_show(m, iommu);  in ir_translation_struct_show()
522 	for_each_active_iommu(iommu, drhd) {  in ir_translation_struct_show()
523 		if (!cap_pi_support(iommu->cap))  in ir_translation_struct_show()
527 			   iommu->name);  in ir_translation_struct_show()
529 		if (iommu->ir_table) {  in ir_translation_struct_show()
530 			irta = virt_to_phys(iommu->ir_table->base);  in ir_translation_struct_show()
532 			ir_tbl_posted_entry_show(m, iommu);  in ir_translation_struct_show()
545 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,  in latency_show_one()  argument
551 		   iommu->name, drhd->reg_base_addr);  in latency_show_one()
553 	ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);  in latency_show_one()
564 	struct intel_iommu *iommu;  in latency_show()  local
567 	for_each_active_iommu(iommu, drhd)  in latency_show()
568 		latency_show_one(m, iommu, drhd);  in latency_show()
584 	struct intel_iommu *iommu;  in dmar_perf_latency_write()  local
602 		for_each_active_iommu(iommu, drhd) {  in dmar_perf_latency_write()
603 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
604 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
605 			dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
606 			dmar_latency_disable(iommu, DMAR_LATENCY_PRQ);  in dmar_perf_latency_write()
612 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
613 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);  in dmar_perf_latency_write()
618 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
619 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);  in dmar_perf_latency_write()
624 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
625 			dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);  in dmar_perf_latency_write()
630 		for_each_active_iommu(iommu, drhd)  in dmar_perf_latency_write()
631 			dmar_latency_enable(iommu, DMAR_LATENCY_PRQ);  in dmar_perf_latency_write()