Lines Matching refs:state
115 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) in tda1004x_write_byteI() argument
123 msg.addr = state->config->demod_address; in tda1004x_write_byteI()
124 ret = i2c_transfer(state->i2c, &msg, 1); in tda1004x_write_byteI()
135 static int tda1004x_read_byte(struct tda1004x_state *state, int reg) in tda1004x_read_byte() argument
145 msg[0].addr = state->config->demod_address; in tda1004x_read_byte()
146 msg[1].addr = state->config->demod_address; in tda1004x_read_byte()
147 ret = i2c_transfer(state->i2c, msg, 2); in tda1004x_read_byte()
160 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) in tda1004x_write_mask() argument
167 val = tda1004x_read_byte(state, reg); in tda1004x_write_mask()
176 return tda1004x_write_byteI(state, reg, val); in tda1004x_write_mask()
179 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) in tda1004x_write_buf() argument
188 result = tda1004x_write_byteI(state, reg + i, buf[i]); in tda1004x_write_buf()
196 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state) in tda1004x_enable_tuner_i2c() argument
201 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); in tda1004x_enable_tuner_i2c()
206 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state) in tda1004x_disable_tuner_i2c() argument
210 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); in tda1004x_disable_tuner_i2c()
213 static int tda10045h_set_bandwidth(struct tda1004x_state *state, in tda10045h_set_bandwidth() argument
222 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); in tda10045h_set_bandwidth()
226 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); in tda10045h_set_bandwidth()
230 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); in tda10045h_set_bandwidth()
237 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0); in tda10045h_set_bandwidth()
242 static int tda10046h_set_bandwidth(struct tda1004x_state *state, in tda10046h_set_bandwidth() argument
254 if ((state->config->if_freq == TDA10046_FREQ_045) || in tda10046h_set_bandwidth()
255 (state->config->if_freq == TDA10046_FREQ_052)) in tda10046h_set_bandwidth()
262 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, in tda10046h_set_bandwidth()
265 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, in tda10046h_set_bandwidth()
267 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
268 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); in tda10046h_set_bandwidth()
269 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); in tda10046h_set_bandwidth()
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, in tda10046h_set_bandwidth()
278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, in tda10046h_set_bandwidth()
280 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046h_set_bandwidth()
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046h_set_bandwidth()
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, in tda10046h_set_bandwidth()
291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, in tda10046h_set_bandwidth()
293 if (state->config->if_freq == TDA10046_FREQ_045) { in tda10046h_set_bandwidth()
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046h_set_bandwidth()
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); in tda10046h_set_bandwidth()
306 static int tda1004x_do_upload(struct tda1004x_state *state, in tda1004x_do_upload() argument
316 tda1004x_write_byteI(state, dspCodeCounterReg, 0); in tda1004x_do_upload()
317 fw_msg.addr = state->config->demod_address; in tda1004x_do_upload()
319 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); in tda1004x_do_upload()
330 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) { in tda1004x_do_upload()
332 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in tda1004x_do_upload()
339 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in tda1004x_do_upload()
347 static int tda1004x_check_upload_ok(struct tda1004x_state *state) in tda1004x_check_upload_ok() argument
352 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { in tda1004x_check_upload_ok()
354 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) { in tda1004x_check_upload_ok()
365 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP in tda1004x_check_upload_ok()
366 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67); in tda1004x_check_upload_ok()
368 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1); in tda1004x_check_upload_ok()
369 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2); in tda1004x_check_upload_ok()
380 struct tda1004x_state* state = fe->demodulator_priv; in tda10045_fwupload() local
385 if (tda1004x_check_upload_ok(state) == 0) in tda10045_fwupload()
390 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); in tda10045_fwupload()
397 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); in tda10045_fwupload()
398 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda10045_fwupload()
399 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda10045_fwupload()
403 tda10045h_set_bandwidth(state, 8000000); in tda10045_fwupload()
405 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); in tda10045_fwupload()
415 return tda1004x_check_upload_ok(state); in tda10045_fwupload()
420 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_init_plls() local
423 if ((state->config->if_freq == TDA10046_FREQ_045) || in tda10046_init_plls()
424 (state->config->if_freq == TDA10046_FREQ_052)) in tda10046_init_plls()
429 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); in tda10046_init_plls()
432 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 in tda10046_init_plls()
435 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 in tda10046_init_plls()
437 if (state->config->xtal_freq == TDA10046_XTAL_4M ) { in tda10046_init_plls()
439 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 in tda10046_init_plls()
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 in tda10046_init_plls()
445 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); in tda10046_init_plls()
447 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); in tda10046_init_plls()
449 switch (state->config->if_freq) { in tda10046_init_plls()
451 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); in tda10046_init_plls()
452 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); in tda10046_init_plls()
455 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); in tda10046_init_plls()
456 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); in tda10046_init_plls()
459 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
460 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); in tda10046_init_plls()
463 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); in tda10046_init_plls()
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); in tda10046_init_plls()
467 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */ in tda10046_init_plls()
474 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_fwupload() local
479 if (state->config->xtal_freq == TDA10046_XTAL_4M) { in tda10046_fwupload()
485 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
487 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); in tda10046_fwupload()
489 if (state->config->gpio_config != TDA10046_GPTRI) { in tda10046_fwupload()
490 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33); in tda10046_fwupload()
491 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); in tda10046_fwupload()
498 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); in tda10046_fwupload()
501 if (tda1004x_check_upload_ok(state) == 0) in tda10046_fwupload()
517 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4); in tda10046_fwupload()
519 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4); in tda10046_fwupload()
522 if (tda1004x_check_upload_ok(state) == 0) in tda10046_fwupload()
527 if (state->config->request_firmware != NULL) { in tda10046_fwupload()
530 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE); in tda10046_fwupload()
533 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); in tda10046_fwupload()
546 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST in tda10046_fwupload()
547 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN); in tda10046_fwupload()
549 return tda1004x_check_upload_ok(state); in tda10046_fwupload()
594 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_write() local
599 return tda1004x_write_byteI(state, buf[0], buf[1]); in tda1004x_write()
604 struct tda1004x_state* state = fe->demodulator_priv; in tda10045_init() local
613 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC in tda10045_init()
616 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10045_init()
617 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream in tda10045_init()
618 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal in tda10045_init()
619 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer in tda10045_init()
620 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset in tda10045_init()
621 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset in tda10045_init()
622 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface in tda10045_init()
623 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface in tda10045_init()
624 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits in tda10045_init()
625 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity in tda10045_init()
626 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e); in tda10045_init()
628 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); in tda10045_init()
635 struct tda1004x_state* state = fe->demodulator_priv; in tda10046_init() local
644 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10046_init()
645 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream in tda10046_init()
646 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer in tda10046_init()
648 switch (state->config->agc_config) { in tda10046_init()
650 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup in tda10046_init()
651 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
654 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
655 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
658 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup in tda10046_init()
659 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities in tda10046_init()
662 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup in tda10046_init()
663 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold in tda10046_init()
664 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize in tda10046_init()
665 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
668 if (state->config->ts_mode == 0) { in tda10046_init()
669 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); in tda10046_init()
670 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); in tda10046_init()
672 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); in tda10046_init()
673 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, in tda10046_init()
674 state->config->invert_oclk << 4); in tda10046_init()
676 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); in tda10046_init()
677 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on in tda10046_init()
678 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } in tda10046_init()
679 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values in tda10046_init()
680 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } in tda10046_init()
681 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } in tda10046_init()
682 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 in tda10046_init()
683 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits in tda10046_init()
684 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config in tda10046_init()
685 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config in tda10046_init()
694 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_set_fe() local
700 if (state->demod_type == TDA1004X_DEMOD_TDA10046) { in tda1004x_set_fe()
702 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); in tda1004x_set_fe()
703 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); in tda1004x_set_fe()
704 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); in tda1004x_set_fe()
707 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); in tda1004x_set_fe()
719 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { in tda1004x_set_fe()
730 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto in tda1004x_set_fe()
731 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ in tda1004x_set_fe()
732 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits in tda1004x_set_fe()
733 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits in tda1004x_set_fe()
735 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto in tda1004x_set_fe()
741 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); in tda1004x_set_fe()
747 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); in tda1004x_set_fe()
752 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); in tda1004x_set_fe()
756 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); in tda1004x_set_fe()
760 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); in tda1004x_set_fe()
770 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); in tda1004x_set_fe()
774 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); in tda1004x_set_fe()
778 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); in tda1004x_set_fe()
782 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); in tda1004x_set_fe()
791 switch (state->demod_type) { in tda1004x_set_fe()
793 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz); in tda1004x_set_fe()
797 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz); in tda1004x_set_fe()
803 if (state->config->invert) in tda1004x_set_fe()
807 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); in tda1004x_set_fe()
811 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); in tda1004x_set_fe()
821 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
822 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); in tda1004x_set_fe()
831 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
832 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); in tda1004x_set_fe()
836 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
837 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); in tda1004x_set_fe()
841 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); in tda1004x_set_fe()
842 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
852 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
853 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); in tda1004x_set_fe()
857 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
858 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); in tda1004x_set_fe()
862 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); in tda1004x_set_fe()
863 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); in tda1004x_set_fe()
871 switch (state->demod_type) { in tda1004x_set_fe()
873 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda1004x_set_fe()
874 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda1004x_set_fe()
878 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); in tda1004x_set_fe()
880 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); in tda1004x_set_fe()
892 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_get_fe() local
897 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); in tda1004x_get_fe()
907 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) in tda1004x_get_fe()
909 if (state->config->invert) in tda1004x_get_fe()
913 switch (state->demod_type) { in tda1004x_get_fe()
915 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { in tda1004x_get_fe()
928 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { in tda1004x_get_fe()
947 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); in tda1004x_get_fe()
949 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); in tda1004x_get_fe()
952 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { in tda1004x_get_fe()
966 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) in tda1004x_get_fe()
970 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { in tda1004x_get_fe()
986 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { in tda1004x_get_fe()
1007 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_status() local
1015 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD); in tda1004x_read_status()
1032 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB); in tda1004x_read_status()
1035 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB); in tda1004x_read_status()
1040 tda1004x_read_byte(state, TDA1004X_CBER_RESET); in tda1004x_read_status()
1050 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB); in tda1004x_read_status()
1053 status = tda1004x_read_byte(state, TDA1004X_VBER_MID); in tda1004x_read_status()
1057 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB); in tda1004x_read_status()
1062 tda1004x_read_byte(state, TDA1004X_CVBER_LUT); in tda1004x_read_status()
1077 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_signal_strength() local
1084 switch (state->demod_type) { in tda1004x_read_signal_strength()
1095 tmp = tda1004x_read_byte(state, reg); in tda1004x_read_signal_strength()
1106 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_snr() local
1112 tmp = tda1004x_read_byte(state, TDA1004X_SNR); in tda1004x_read_snr()
1124 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_ucblocks() local
1133 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR); in tda1004x_read_ucblocks()
1138 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1139 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1140 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1142 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR); in tda1004x_read_ucblocks()
1161 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_read_ber() local
1167 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB); in tda1004x_read_ber()
1171 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB); in tda1004x_read_ber()
1176 tda1004x_read_byte(state, TDA1004X_CBER_RESET); in tda1004x_read_ber()
1184 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_sleep() local
1187 switch (state->demod_type) { in tda1004x_sleep()
1189 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); in tda1004x_sleep()
1194 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff); in tda1004x_sleep()
1196 gpio_conf = state->config->gpio_config; in tda1004x_sleep()
1198 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, in tda1004x_sleep()
1201 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); in tda1004x_sleep()
1202 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); in tda1004x_sleep()
1211 struct tda1004x_state* state = fe->demodulator_priv; in tda1004x_i2c_gate_ctrl() local
1214 return tda1004x_enable_tuner_i2c(state); in tda1004x_i2c_gate_ctrl()
1216 return tda1004x_disable_tuner_i2c(state); in tda1004x_i2c_gate_ctrl()
1231 struct tda1004x_state *state = fe->demodulator_priv; in tda1004x_release() local
1232 kfree(state); in tda1004x_release()
1270 struct tda1004x_state *state; in tda10045_attach() local
1274 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); in tda10045_attach()
1275 if (!state) { in tda10045_attach()
1281 state->config = config; in tda10045_attach()
1282 state->i2c = i2c; in tda10045_attach()
1283 state->demod_type = TDA1004X_DEMOD_TDA10045; in tda10045_attach()
1286 id = tda1004x_read_byte(state, TDA1004X_CHIPID); in tda10045_attach()
1289 kfree(state); in tda10045_attach()
1295 kfree(state); in tda10045_attach()
1300 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops)); in tda10045_attach()
1301 state->frontend.demodulator_priv = state; in tda10045_attach()
1302 return &state->frontend; in tda10045_attach()
1340 struct tda1004x_state *state; in tda10046_attach() local
1344 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL); in tda10046_attach()
1345 if (!state) { in tda10046_attach()
1351 state->config = config; in tda10046_attach()
1352 state->i2c = i2c; in tda10046_attach()
1353 state->demod_type = TDA1004X_DEMOD_TDA10046; in tda10046_attach()
1356 id = tda1004x_read_byte(state, TDA1004X_CHIPID); in tda10046_attach()
1359 kfree(state); in tda10046_attach()
1364 kfree(state); in tda10046_attach()
1369 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops)); in tda10046_attach()
1370 state->frontend.demodulator_priv = state; in tda10046_attach()
1371 return &state->frontend; in tda10046_attach()