Lines Matching refs:inter
249 static int netup_fpga_op_rw(struct fpga_internal *inter, int addr, in netup_fpga_op_rw() argument
252 inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0); in netup_fpga_op_rw()
253 return inter->fpga_rw(inter->dev, 0, val, read); in netup_fpga_op_rw()
262 struct fpga_internal *inter = state->internal; in altera_ci_op_cam() local
270 mutex_lock(&inter->fpga_mutex); in altera_ci_op_cam()
272 netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0); in altera_ci_op_cam()
273 netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0); in altera_ci_op_cam()
274 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_op_cam()
279 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0); in altera_ci_op_cam()
280 mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read); in altera_ci_op_cam()
282 mutex_unlock(&inter->fpga_mutex); in altera_ci_op_cam()
320 struct fpga_internal *inter = state->internal; in altera_ci_slot_reset() local
330 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_reset()
332 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_reset()
333 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
336 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_reset()
341 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_reset()
343 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
345 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_reset()
369 struct fpga_internal *inter = state->internal; in altera_ci_slot_ts_ctl() local
377 mutex_lock(&inter->fpga_mutex); in altera_ci_slot_ts_ctl()
379 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_ts_ctl()
380 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_ts_ctl()
383 mutex_unlock(&inter->fpga_mutex); in altera_ci_slot_ts_ctl()
391 struct fpga_internal *inter = in netup_read_ci_status() local
397 mutex_lock(&inter->fpga_mutex); in netup_read_ci_status()
399 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
400 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
402 mutex_unlock(&inter->fpga_mutex); in netup_read_ci_status()
404 if (inter->state[1] != NULL) { in netup_read_ci_status()
405 inter->state[1]->status = in netup_read_ci_status()
410 __func__, inter->state[1]->status); in netup_read_ci_status()
413 if (inter->state[0] != NULL) { in netup_read_ci_status()
414 inter->state[0]->status = in netup_read_ci_status()
419 __func__, inter->state[0]->status); in netup_read_ci_status()
427 struct fpga_internal *inter = NULL; in altera_ci_irq() local
434 inter = temp_int->internal; in altera_ci_irq()
435 schedule_work(&inter->work); in altera_ci_irq()
517 struct fpga_internal *inter = pid_filt->internal; in altera_pid_control() local
524 mutex_lock(&inter->fpga_mutex); in altera_pid_control()
526 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0); in altera_pid_control()
527 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_pid_control()
530 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD); in altera_pid_control()
537 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0); in altera_pid_control()
539 mutex_unlock(&inter->fpga_mutex); in altera_pid_control()
548 struct fpga_internal *inter = pid_filt->internal; in altera_toggle_fullts_streaming() local
560 mutex_lock(&inter->fpga_mutex); in altera_toggle_fullts_streaming()
563 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0); in altera_toggle_fullts_streaming()
565 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_toggle_fullts_streaming()
568 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, in altera_toggle_fullts_streaming()
572 mutex_unlock(&inter->fpga_mutex); in altera_toggle_fullts_streaming()
579 struct fpga_internal *inter = temp_int->internal; in altera_pid_feed_control() local
580 struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1]; in altera_pid_feed_control()
634 struct fpga_internal *inter = NULL; in altera_hw_filt_init() local
647 inter = temp_int->internal; in altera_hw_filt_init()
648 (inter->filts_used)++; in altera_hw_filt_init()
651 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); in altera_hw_filt_init()
652 if (!inter) { in altera_hw_filt_init()
657 temp_int = append_internal(inter); in altera_hw_filt_init()
662 inter->filts_used = 1; in altera_hw_filt_init()
663 inter->dev = config->dev; in altera_hw_filt_init()
664 inter->fpga_rw = config->fpga_rw; in altera_hw_filt_init()
665 mutex_init(&inter->fpga_mutex); in altera_hw_filt_init()
666 inter->strt_wrk = 1; in altera_hw_filt_init()
672 inter->pid_filt[hw_filt_nr - 1] = pid_filt; in altera_hw_filt_init()
674 pid_filt->internal = inter; in altera_hw_filt_init()
696 kfree(inter); in altera_hw_filt_init()
705 struct fpga_internal *inter = NULL; in altera_ci_init() local
719 inter = temp_int->internal; in altera_ci_init()
720 (inter->cis_used)++; in altera_ci_init()
721 inter->fpga_rw = config->fpga_rw; in altera_ci_init()
724 inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL); in altera_ci_init()
725 if (!inter) { in altera_ci_init()
730 temp_int = append_internal(inter); in altera_ci_init()
735 inter->cis_used = 1; in altera_ci_init()
736 inter->dev = config->dev; in altera_ci_init()
737 inter->fpga_rw = config->fpga_rw; in altera_ci_init()
738 mutex_init(&inter->fpga_mutex); in altera_ci_init()
739 inter->strt_wrk = 1; in altera_ci_init()
745 state->internal = inter; in altera_ci_init()
766 inter->state[ci_nr - 1] = state; in altera_ci_init()
770 if (inter->strt_wrk) { in altera_ci_init()
771 INIT_WORK(&inter->work, netup_read_ci_status); in altera_ci_init()
772 inter->strt_wrk = 0; in altera_ci_init()
777 mutex_lock(&inter->fpga_mutex); in altera_ci_init()
780 netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0); in altera_ci_init()
781 netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0); in altera_ci_init()
784 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_init()
786 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_init()
788 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD); in altera_ci_init()
790 netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0); in altera_ci_init()
792 mutex_unlock(&inter->fpga_mutex); in altera_ci_init()
796 schedule_work(&inter->work); in altera_ci_init()
803 kfree(inter); in altera_ci_init()
812 struct fpga_internal *inter = NULL; in altera_ci_tuner_reset() local
823 inter = temp_int->internal; in altera_ci_tuner_reset()
825 mutex_lock(&inter->fpga_mutex); in altera_ci_tuner_reset()
827 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_tuner_reset()
829 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()
832 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()
834 mutex_unlock(&inter->fpga_mutex); in altera_ci_tuner_reset()