Lines Matching refs:vin
146 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset) in rvin_write() argument
148 iowrite32(value, vin->base + offset); in rvin_write()
151 static u32 rvin_read(struct rvin_dev *vin, u32 offset) in rvin_read() argument
153 return ioread32(vin->base + offset); in rvin_read()
478 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs) in rvin_set_coeff() argument
499 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
500 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG); in rvin_set_coeff()
501 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG); in rvin_set_coeff()
503 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG); in rvin_set_coeff()
504 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG); in rvin_set_coeff()
505 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG); in rvin_set_coeff()
507 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG); in rvin_set_coeff()
508 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG); in rvin_set_coeff()
509 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG); in rvin_set_coeff()
511 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG); in rvin_set_coeff()
512 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG); in rvin_set_coeff()
513 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG); in rvin_set_coeff()
515 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG); in rvin_set_coeff()
516 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG); in rvin_set_coeff()
517 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG); in rvin_set_coeff()
519 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG); in rvin_set_coeff()
520 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG); in rvin_set_coeff()
521 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG); in rvin_set_coeff()
523 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG); in rvin_set_coeff()
524 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG); in rvin_set_coeff()
525 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG); in rvin_set_coeff()
527 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG); in rvin_set_coeff()
528 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG); in rvin_set_coeff()
529 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG); in rvin_set_coeff()
532 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin) in rvin_crop_scale_comp_gen2() argument
538 crop_height = vin->crop.height; in rvin_crop_scale_comp_gen2()
539 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
543 if (crop_height != vin->compose.height) in rvin_crop_scale_comp_gen2()
544 ys = (4096 * crop_height) / vin->compose.height; in rvin_crop_scale_comp_gen2()
545 rvin_write(vin, ys, VNYS_REG); in rvin_crop_scale_comp_gen2()
548 if (vin->crop.width != vin->compose.width) in rvin_crop_scale_comp_gen2()
549 xs = (4096 * vin->crop.width) / vin->compose.width; in rvin_crop_scale_comp_gen2()
555 rvin_write(vin, xs, VNXS_REG); in rvin_crop_scale_comp_gen2()
561 rvin_set_coeff(vin, xs); in rvin_crop_scale_comp_gen2()
564 rvin_write(vin, 0, VNSPPOC_REG); in rvin_crop_scale_comp_gen2()
565 rvin_write(vin, 0, VNSLPOC_REG); in rvin_crop_scale_comp_gen2()
566 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG); in rvin_crop_scale_comp_gen2()
568 if (V4L2_FIELD_HAS_BOTH(vin->format.field)) in rvin_crop_scale_comp_gen2()
569 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
571 rvin_write(vin, vin->format.height - 1, VNELPOC_REG); in rvin_crop_scale_comp_gen2()
573 vin_dbg(vin, in rvin_crop_scale_comp_gen2()
575 vin->crop.width, vin->crop.height, vin->crop.left, in rvin_crop_scale_comp_gen2()
576 vin->crop.top, ys, xs, vin->format.width, vin->format.height, in rvin_crop_scale_comp_gen2()
580 void rvin_crop_scale_comp(struct rvin_dev *vin) in rvin_crop_scale_comp() argument
586 rvin_write(vin, vin->crop.left, VNSPPRC_REG); in rvin_crop_scale_comp()
587 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG); in rvin_crop_scale_comp()
588 rvin_write(vin, vin->crop.top, VNSLPRC_REG); in rvin_crop_scale_comp()
589 rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG); in rvin_crop_scale_comp()
592 if (vin->info->model != RCAR_GEN3) in rvin_crop_scale_comp()
593 rvin_crop_scale_comp_gen2(vin); in rvin_crop_scale_comp()
595 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_crop_scale_comp()
596 stride = vin->format.bytesperline / fmt->bpp; in rvin_crop_scale_comp()
601 switch (vin->format.pixelformat) { in rvin_crop_scale_comp()
612 rvin_write(vin, stride, VNIS_REG); in rvin_crop_scale_comp()
619 static int rvin_setup(struct rvin_dev *vin) in rvin_setup() argument
624 switch (vin->format.field) { in rvin_setup()
635 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60) in rvin_setup()
659 switch (vin->mbus_code) { in rvin_setup()
671 if (!vin->is_csi && in rvin_setup()
672 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
684 if (!vin->is_csi && in rvin_setup()
685 vin->parallel.mbus_type == V4L2_MBUS_BT656) in rvin_setup()
703 if (vin->info->model == RCAR_GEN3) in rvin_setup()
708 if (!vin->is_csi) { in rvin_setup()
710 if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) in rvin_setup()
714 if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) in rvin_setup()
718 if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW) in rvin_setup()
721 switch (vin->mbus_code) { in rvin_setup()
723 if (vin->parallel.bus.bus_width == 8 && in rvin_setup()
724 vin->parallel.bus.data_shift == 8) in rvin_setup()
735 switch (vin->format.pixelformat) { in rvin_setup()
738 rvin_write(vin, in rvin_setup()
739 ALIGN(vin->format.bytesperline * vin->format.height, in rvin_setup()
741 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ? in rvin_setup()
764 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
767 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB; in rvin_setup()
776 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
777 vin->format.pixelformat); in rvin_setup()
788 if (vin->info->model == RCAR_GEN3) { in rvin_setup()
790 if (vin->is_csi) in rvin_setup()
800 rvin_write(vin, interrupts, VNINTS_REG); in rvin_setup()
802 rvin_write(vin, interrupts, VNIE_REG); in rvin_setup()
804 rvin_write(vin, dmr, VNDMR_REG); in rvin_setup()
805 rvin_write(vin, dmr2, VNDMR2_REG); in rvin_setup()
808 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG); in rvin_setup()
813 static void rvin_disable_interrupts(struct rvin_dev *vin) in rvin_disable_interrupts() argument
815 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
818 static u32 rvin_get_interrupt_status(struct rvin_dev *vin) in rvin_get_interrupt_status() argument
820 return rvin_read(vin, VNINTS_REG); in rvin_get_interrupt_status()
823 static void rvin_ack_interrupt(struct rvin_dev *vin) in rvin_ack_interrupt() argument
825 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG); in rvin_ack_interrupt()
828 static bool rvin_capture_active(struct rvin_dev *vin) in rvin_capture_active() argument
830 return rvin_read(vin, VNMS_REG) & VNMS_CA; in rvin_capture_active()
833 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms) in rvin_get_active_field() argument
835 if (vin->format.field == V4L2_FIELD_ALTERNATE) { in rvin_get_active_field()
842 return vin->format.field; in rvin_get_active_field()
845 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr) in rvin_set_slot_addr() argument
851 fmt = rvin_format_from_pixel(vin, vin->format.pixelformat); in rvin_set_slot_addr()
857 offsetx = vin->compose.left * fmt->bpp; in rvin_set_slot_addr()
858 offsety = vin->compose.top * vin->format.bytesperline; in rvin_set_slot_addr()
868 rvin_write(vin, offset, VNMB_REG(slot)); in rvin_set_slot_addr()
877 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot) in rvin_fill_hw_slot() argument
885 if (WARN_ON(vin->buf_hw[slot].buffer)) in rvin_fill_hw_slot()
890 if (vin->buf_hw[prev].type == HALF_TOP) { in rvin_fill_hw_slot()
891 vbuf = vin->buf_hw[prev].buffer; in rvin_fill_hw_slot()
892 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
893 vin->buf_hw[slot].type = HALF_BOTTOM; in rvin_fill_hw_slot()
894 switch (vin->format.pixelformat) { in rvin_fill_hw_slot()
897 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
898 vin->format.sizeimage / 4; in rvin_fill_hw_slot()
901 phys_addr = vin->buf_hw[prev].phys + in rvin_fill_hw_slot()
902 vin->format.sizeimage / 2; in rvin_fill_hw_slot()
905 } else if ((vin->state != STOPPED && vin->state != RUNNING) || in rvin_fill_hw_slot()
906 list_empty(&vin->buf_list)) { in rvin_fill_hw_slot()
907 vin->buf_hw[slot].buffer = NULL; in rvin_fill_hw_slot()
908 vin->buf_hw[slot].type = FULL; in rvin_fill_hw_slot()
909 phys_addr = vin->scratch_phys; in rvin_fill_hw_slot()
912 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list); in rvin_fill_hw_slot()
915 vin->buf_hw[slot].buffer = vbuf; in rvin_fill_hw_slot()
917 vin->buf_hw[slot].type = in rvin_fill_hw_slot()
918 V4L2_FIELD_IS_SEQUENTIAL(vin->format.field) ? in rvin_fill_hw_slot()
925 vin_dbg(vin, "Filling HW slot: %d type: %d buffer: %p\n", in rvin_fill_hw_slot()
926 slot, vin->buf_hw[slot].type, vin->buf_hw[slot].buffer); in rvin_fill_hw_slot()
928 vin->buf_hw[slot].phys = phys_addr; in rvin_fill_hw_slot()
929 rvin_set_slot_addr(vin, slot, phys_addr); in rvin_fill_hw_slot()
932 static int rvin_capture_start(struct rvin_dev *vin) in rvin_capture_start() argument
937 vin->buf_hw[slot].buffer = NULL; in rvin_capture_start()
938 vin->buf_hw[slot].type = FULL; in rvin_capture_start()
942 rvin_fill_hw_slot(vin, slot); in rvin_capture_start()
944 rvin_crop_scale_comp(vin); in rvin_capture_start()
946 ret = rvin_setup(vin); in rvin_capture_start()
950 vin_dbg(vin, "Starting to capture\n"); in rvin_capture_start()
953 rvin_write(vin, VNFC_C_FRAME, VNFC_REG); in rvin_capture_start()
955 vin->state = STARTING; in rvin_capture_start()
960 static void rvin_capture_stop(struct rvin_dev *vin) in rvin_capture_stop() argument
963 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
966 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG); in rvin_capture_stop()
978 struct rvin_dev *vin = data; in rvin_irq() local
984 spin_lock_irqsave(&vin->qlock, flags); in rvin_irq()
986 int_status = rvin_get_interrupt_status(vin); in rvin_irq()
990 rvin_ack_interrupt(vin); in rvin_irq()
994 if (vin->state == STOPPED) { in rvin_irq()
995 vin_dbg(vin, "IRQ while state stopped\n"); in rvin_irq()
1000 vnms = rvin_read(vin, VNMS_REG); in rvin_irq()
1007 if (vin->state == STARTING) { in rvin_irq()
1009 vin_dbg(vin, "Starting sync slot: %d\n", slot); in rvin_irq()
1013 vin_dbg(vin, "Capture start synced!\n"); in rvin_irq()
1014 vin->state = RUNNING; in rvin_irq()
1018 if (vin->buf_hw[slot].buffer) { in rvin_irq()
1023 if (vin->buf_hw[slot].type == HALF_TOP) { in rvin_irq()
1024 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1025 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1029 vin->buf_hw[slot].buffer->field = in rvin_irq()
1030 rvin_get_active_field(vin, vnms); in rvin_irq()
1031 vin->buf_hw[slot].buffer->sequence = vin->sequence; in rvin_irq()
1032 vin->buf_hw[slot].buffer->vb2_buf.timestamp = ktime_get_ns(); in rvin_irq()
1033 vb2_buffer_done(&vin->buf_hw[slot].buffer->vb2_buf, in rvin_irq()
1035 vin->buf_hw[slot].buffer = NULL; in rvin_irq()
1038 vin_dbg(vin, "Dropping frame %u\n", vin->sequence); in rvin_irq()
1041 vin->sequence++; in rvin_irq()
1044 rvin_fill_hw_slot(vin, slot); in rvin_irq()
1046 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_irq()
1051 static void return_unused_buffers(struct rvin_dev *vin, in return_unused_buffers() argument
1057 spin_lock_irqsave(&vin->qlock, flags); in return_unused_buffers()
1059 list_for_each_entry_safe(buf, node, &vin->buf_list, list) { in return_unused_buffers()
1064 spin_unlock_irqrestore(&vin->qlock, flags); in return_unused_buffers()
1072 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_queue_setup() local
1076 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1079 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1086 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_prepare() local
1087 unsigned long size = vin->format.sizeimage; in rvin_buffer_prepare()
1090 vin_err(vin, "buffer too small (%lu < %lu)\n", in rvin_buffer_prepare()
1103 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue); in rvin_buffer_queue() local
1106 spin_lock_irqsave(&vin->qlock, flags); in rvin_buffer_queue()
1108 list_add_tail(to_buf_list(vbuf), &vin->buf_list); in rvin_buffer_queue()
1110 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_buffer_queue()
1113 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd, in rvin_mc_validate_format() argument
1132 if (vin->format.pixelformat != V4L2_PIX_FMT_SBGGR8) in rvin_mc_validate_format()
1136 if (vin->format.pixelformat != V4L2_PIX_FMT_SGBRG8) in rvin_mc_validate_format()
1140 if (vin->format.pixelformat != V4L2_PIX_FMT_SGRBG8) in rvin_mc_validate_format()
1144 if (vin->format.pixelformat != V4L2_PIX_FMT_SRGGB8) in rvin_mc_validate_format()
1150 vin->mbus_code = fmt.format.code; in rvin_mc_validate_format()
1164 switch (vin->format.field) { in rvin_mc_validate_format()
1186 if (fmt.format.width != vin->format.width || in rvin_mc_validate_format()
1187 fmt.format.height != vin->format.height || in rvin_mc_validate_format()
1188 fmt.format.code != vin->mbus_code) in rvin_mc_validate_format()
1194 static int rvin_set_stream(struct rvin_dev *vin, int on) in rvin_set_stream() argument
1203 if (!vin->info->use_mc) { in rvin_set_stream()
1204 ret = v4l2_subdev_call(vin->parallel.subdev, video, s_stream, in rvin_set_stream()
1210 pad = media_entity_remote_pad(&vin->pad); in rvin_set_stream()
1217 media_pipeline_stop(&vin->vdev.entity); in rvin_set_stream()
1221 ret = rvin_mc_validate_format(vin, sd, pad); in rvin_set_stream()
1231 mdev = vin->vdev.entity.graph_obj.mdev; in rvin_set_stream()
1233 pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe; in rvin_set_stream()
1234 ret = __media_pipeline_start(&vin->vdev.entity, pipe); in rvin_set_stream()
1243 media_pipeline_stop(&vin->vdev.entity); in rvin_set_stream()
1248 int rvin_start_streaming(struct rvin_dev *vin) in rvin_start_streaming() argument
1253 ret = rvin_set_stream(vin, 1); in rvin_start_streaming()
1257 spin_lock_irqsave(&vin->qlock, flags); in rvin_start_streaming()
1259 vin->sequence = 0; in rvin_start_streaming()
1261 ret = rvin_capture_start(vin); in rvin_start_streaming()
1263 rvin_set_stream(vin, 0); in rvin_start_streaming()
1265 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_start_streaming()
1272 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_start_streaming_vq() local
1276 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage, in rvin_start_streaming_vq()
1277 &vin->scratch_phys, GFP_KERNEL); in rvin_start_streaming_vq()
1278 if (!vin->scratch) in rvin_start_streaming_vq()
1281 ret = rvin_start_streaming(vin); in rvin_start_streaming_vq()
1287 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_start_streaming_vq()
1288 vin->scratch_phys); in rvin_start_streaming_vq()
1290 return_unused_buffers(vin, VB2_BUF_STATE_QUEUED); in rvin_start_streaming_vq()
1295 void rvin_stop_streaming(struct rvin_dev *vin) in rvin_stop_streaming() argument
1301 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1303 if (vin->state == STOPPED) { in rvin_stop_streaming()
1304 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1308 vin->state = STOPPING; in rvin_stop_streaming()
1315 if (vin->buf_hw[i].buffer) in rvin_stop_streaming()
1321 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1323 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1330 rvin_capture_stop(vin); in rvin_stop_streaming()
1333 if (!rvin_capture_active(vin)) { in rvin_stop_streaming()
1334 vin->state = STOPPED; in rvin_stop_streaming()
1338 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1340 spin_lock_irqsave(&vin->qlock, flags); in rvin_stop_streaming()
1343 if (!buffersFreed || vin->state != STOPPED) { in rvin_stop_streaming()
1349 vin_err(vin, "Failed stop HW, something is seriously broken\n"); in rvin_stop_streaming()
1350 vin->state = STOPPED; in rvin_stop_streaming()
1353 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_stop_streaming()
1355 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1358 rvin_disable_interrupts(vin); in rvin_stop_streaming()
1363 struct rvin_dev *vin = vb2_get_drv_priv(vq); in rvin_stop_streaming_vq() local
1365 rvin_stop_streaming(vin); in rvin_stop_streaming_vq()
1368 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch, in rvin_stop_streaming_vq()
1369 vin->scratch_phys); in rvin_stop_streaming_vq()
1371 return_unused_buffers(vin, VB2_BUF_STATE_ERROR); in rvin_stop_streaming_vq()
1384 void rvin_dma_unregister(struct rvin_dev *vin) in rvin_dma_unregister() argument
1386 mutex_destroy(&vin->lock); in rvin_dma_unregister()
1388 v4l2_device_unregister(&vin->v4l2_dev); in rvin_dma_unregister()
1391 int rvin_dma_register(struct rvin_dev *vin, int irq) in rvin_dma_register() argument
1393 struct vb2_queue *q = &vin->queue; in rvin_dma_register()
1397 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev); in rvin_dma_register()
1401 mutex_init(&vin->lock); in rvin_dma_register()
1402 INIT_LIST_HEAD(&vin->buf_list); in rvin_dma_register()
1404 spin_lock_init(&vin->qlock); in rvin_dma_register()
1406 vin->state = STOPPED; in rvin_dma_register()
1409 vin->buf_hw[i].buffer = NULL; in rvin_dma_register()
1414 q->lock = &vin->lock; in rvin_dma_register()
1415 q->drv_priv = vin; in rvin_dma_register()
1421 q->dev = vin->dev; in rvin_dma_register()
1425 vin_err(vin, "failed to initialize VB2 queue\n"); in rvin_dma_register()
1430 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED, in rvin_dma_register()
1431 KBUILD_MODNAME, vin); in rvin_dma_register()
1433 vin_err(vin, "failed to request irq\n"); in rvin_dma_register()
1439 rvin_dma_unregister(vin); in rvin_dma_register()
1453 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) in rvin_set_channel_routing() argument
1460 ret = pm_runtime_resume_and_get(vin->dev); in rvin_set_channel_routing()
1465 vnmc = rvin_read(vin, VNMC_REG); in rvin_set_channel_routing()
1466 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); in rvin_set_channel_routing()
1474 for (route = vin->info->routes; route->mask; route++) { in rvin_set_channel_routing()
1486 rvin_write(vin, ifmd, VNCSI_IFMD_REG); in rvin_set_channel_routing()
1489 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1491 vin->chsel = chsel; in rvin_set_channel_routing()
1494 rvin_write(vin, vnmc, VNMC_REG); in rvin_set_channel_routing()
1496 pm_runtime_put(vin->dev); in rvin_set_channel_routing()
1501 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha) in rvin_set_alpha() argument
1506 spin_lock_irqsave(&vin->qlock, flags); in rvin_set_alpha()
1508 vin->alpha = alpha; in rvin_set_alpha()
1510 if (vin->state == STOPPED) in rvin_set_alpha()
1513 switch (vin->format.pixelformat) { in rvin_set_alpha()
1515 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT; in rvin_set_alpha()
1516 if (vin->alpha) in rvin_set_alpha()
1520 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK; in rvin_set_alpha()
1521 dmr |= VNDMR_A8BIT(vin->alpha); in rvin_set_alpha()
1527 rvin_write(vin, dmr, VNDMR_REG); in rvin_set_alpha()
1529 spin_unlock_irqrestore(&vin->qlock, flags); in rvin_set_alpha()