Lines Matching refs:pcr
16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) in rts5249_get_ic_version() argument
20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5249_get_ic_version()
24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5249_fill_driving() argument
42 drive_sel = pcr->sd30_drive_sel_3v3; in rts5249_fill_driving()
45 drive_sel = pcr->sd30_drive_sel_1v8; in rts5249_fill_driving()
48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, in rts5249_fill_driving()
50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, in rts5249_fill_driving()
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, in rts5249_fill_driving()
56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx_base_fetch_vendor_settings() argument
58 struct pci_dev *pdev = pcr->pci; in rtsx_base_fetch_vendor_settings()
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx_base_fetch_vendor_settings()
65 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx_base_fetch_vendor_settings()
69 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx_base_fetch_vendor_settings()
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx_base_fetch_vendor_settings()
71 pcr->card_drive_sel &= 0x3F; in rtsx_base_fetch_vendor_settings()
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); in rtsx_base_fetch_vendor_settings()
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx_base_fetch_vendor_settings()
77 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg); in rtsx_base_fetch_vendor_settings()
80 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; in rtsx_base_fetch_vendor_settings()
81 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx_base_fetch_vendor_settings()
83 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx_base_fetch_vendor_settings()
86 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) in rts5249_init_from_cfg() argument
88 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_cfg()
90 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_init_from_cfg()
91 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5249_init_from_cfg()
93 rtsx_pci_disable_oobs_polling(pcr); in rts5249_init_from_cfg()
95 rtsx_pci_enable_oobs_polling(pcr); in rts5249_init_from_cfg()
100 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5249_init_from_cfg()
104 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) in rts52xa_save_content_from_efuse() argument
112 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
116 pcr_dbg(pcr, "Enable efuse por!"); in rts52xa_save_content_from_efuse()
117 pcr_dbg(pcr, "save efuse to autoload"); in rts52xa_save_content_from_efuse()
119 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); in rts52xa_save_content_from_efuse()
120 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
124 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
128 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
134 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
136 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
140 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
144 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
145 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
148 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_from_efuse()
149 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
150 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_from_efuse()
151 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_from_efuse()
156 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
159 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, in rts52xa_save_content_from_efuse()
161 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, in rts52xa_save_content_from_efuse()
165 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); in rts52xa_save_content_from_efuse()
169 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); in rts52xa_save_content_from_efuse()
170 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); in rts52xa_save_content_from_efuse()
172 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); in rts52xa_save_content_from_efuse()
173 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_from_efuse()
175 pcr_dbg(pcr, "Disable efuse por!"); in rts52xa_save_content_from_efuse()
178 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) in rts52xa_save_content_to_autoload_space() argument
182 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); in rts52xa_save_content_to_autoload_space()
184 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); in rts52xa_save_content_to_autoload_space()
186 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, in rts52xa_save_content_to_autoload_space()
189 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts52xa_save_content_to_autoload_space()
192 pcr_dbg(pcr, "Power ON efuse!"); in rts52xa_save_content_to_autoload_space()
194 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
196 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); in rts52xa_save_content_to_autoload_space()
198 rts52xa_save_content_from_efuse(pcr); in rts52xa_save_content_to_autoload_space()
201 pcr_dbg(pcr, "Load from autoload"); in rts52xa_save_content_to_autoload_space()
202 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); in rts52xa_save_content_to_autoload_space()
203 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); in rts52xa_save_content_to_autoload_space()
204 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
205 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); in rts52xa_save_content_to_autoload_space()
206 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); in rts52xa_save_content_to_autoload_space()
210 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) in rts5249_extra_init_hw() argument
212 struct rtsx_cr_option *option = &(pcr->option); in rts5249_extra_init_hw()
214 rts5249_init_from_cfg(pcr); in rts5249_extra_init_hw()
216 rtsx_pci_init_cmd(pcr); in rts5249_extra_init_hw()
218 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
219 rts52xa_save_content_to_autoload_space(pcr); in rts5249_extra_init_hw()
222 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); in rts5249_extra_init_hw()
224 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); in rts5249_extra_init_hw()
226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); in rts5249_extra_init_hw()
228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); in rts5249_extra_init_hw()
229 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); in rts5249_extra_init_hw()
231 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); in rts5249_extra_init_hw()
233 rts5249_fill_driving(pcr, OUTPUT_3V3); in rts5249_extra_init_hw()
234 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5249_extra_init_hw()
235 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); in rts5249_extra_init_hw()
237 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); in rts5249_extra_init_hw()
239 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); in rts5249_extra_init_hw()
241 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) in rts5249_extra_init_hw()
242 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); in rts5249_extra_init_hw()
244 if (pcr->rtd3_en) { in rts5249_extra_init_hw()
245 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
246 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
247 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30); in rts5249_extra_init_hw()
249 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01); in rts5249_extra_init_hw()
250 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33); in rts5249_extra_init_hw()
253 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
254 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
255 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); in rts5249_extra_init_hw()
257 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); in rts5249_extra_init_hw()
258 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); in rts5249_extra_init_hw()
268 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
271 rtsx_pci_write_register(pcr, PETXCFG, in rts5249_extra_init_hw()
274 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); in rts5249_extra_init_hw()
275 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { in rts5249_extra_init_hw()
276 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, in rts5249_extra_init_hw()
278 pcr_dbg(pcr, "Power OFF efuse!"); in rts5249_extra_init_hw()
284 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) in rts5249_optimize_phy() argument
288 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); in rts5249_optimize_phy()
292 err = rtsx_pci_write_phy_register(pcr, PHY_REV, in rts5249_optimize_phy()
303 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, in rts5249_optimize_phy()
309 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts5249_optimize_phy()
316 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, in rts5249_optimize_phy()
323 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, in rts5249_optimize_phy()
330 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, in rts5249_optimize_phy()
334 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, in rts5249_optimize_phy()
338 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, in rts5249_optimize_phy()
344 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, in rts5249_optimize_phy()
350 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) in rtsx_base_turn_on_led() argument
352 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); in rtsx_base_turn_on_led()
355 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) in rtsx_base_turn_off_led() argument
357 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); in rtsx_base_turn_off_led()
360 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_enable_auto_blink() argument
362 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); in rtsx_base_enable_auto_blink()
365 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_disable_auto_blink() argument
367 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); in rtsx_base_disable_auto_blink()
370 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_on() argument
373 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_on()
376 rtsx_pci_enable_ocp(pcr); in rtsx_base_card_power_on()
378 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
379 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
381 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
383 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
389 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
390 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
394 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
397 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_off() argument
399 struct rtsx_cr_option *option = &pcr->option; in rtsx_base_card_power_off()
402 rtsx_pci_disable_ocp(pcr); in rtsx_base_card_power_off()
404 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); in rtsx_base_card_power_off()
406 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); in rtsx_base_card_power_off()
410 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_base_switch_output_voltage() argument
417 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
424 if (CHK_PCI_PID(pcr, 0x5249)) { in rtsx_base_switch_output_voltage()
425 err = rtsx_pci_update_phy(pcr, PHY_BACR, in rtsx_base_switch_output_voltage()
432 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
438 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); in rtsx_base_switch_output_voltage()
443 rtsx_pci_init_cmd(pcr); in rtsx_base_switch_output_voltage()
444 rts5249_fill_driving(pcr, voltage); in rtsx_base_switch_output_voltage()
445 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_switch_output_voltage()
513 void rts5249_init_params(struct rtsx_pcr *pcr) in rts5249_init_params() argument
515 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_params()
517 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5249_init_params()
518 pcr->num_slots = 2; in rts5249_init_params()
519 pcr->ops = &rts5249_pcr_ops; in rts5249_init_params()
521 pcr->flags = 0; in rts5249_init_params()
522 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5249_init_params()
523 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
524 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
525 pcr->aspm_en = ASPM_L1_EN; in rts5249_init_params()
526 pcr->aspm_mode = ASPM_MODE_CFG; in rts5249_init_params()
527 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); in rts5249_init_params()
528 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5249_init_params()
530 pcr->ic_version = rts5249_get_ic_version(pcr); in rts5249_init_params()
531 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; in rts5249_init_params()
532 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; in rts5249_init_params()
533 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; in rts5249_init_params()
534 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; in rts5249_init_params()
536 pcr->reg_pm_ctrl3 = PM_CTRL3; in rts5249_init_params()
552 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) in rts524a_write_phy() argument
556 return __rtsx_pci_write_phy_register(pcr, addr, val); in rts524a_write_phy()
559 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rts524a_read_phy() argument
563 return __rtsx_pci_read_phy_register(pcr, addr, val); in rts524a_read_phy()
566 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) in rts524a_optimize_phy() argument
570 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts524a_optimize_phy()
575 rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts524a_optimize_phy()
578 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
581 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_optimize_phy()
582 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
584 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, in rts524a_optimize_phy()
587 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, in rts524a_optimize_phy()
590 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, in rts524a_optimize_phy()
592 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, in rts524a_optimize_phy()
602 rtsx_pci_write_phy_register(pcr, PHY_ANA08, in rts524a_optimize_phy()
609 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) in rts524a_extra_init_hw() argument
611 rts5249_extra_init_hw(pcr); in rts524a_extra_init_hw()
613 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts524a_extra_init_hw()
615 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts524a_extra_init_hw()
616 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, in rts524a_extra_init_hw()
618 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts524a_extra_init_hw()
619 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_extra_init_hw()
620 rtsx_pci_write_register(pcr, LDO_DV18_CFG, in rts524a_extra_init_hw()
622 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts524a_extra_init_hw()
624 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
626 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
628 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts524a_extra_init_hw()
630 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, in rts524a_extra_init_hw()
637 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5250_set_l1off_cfg_sub_d0() argument
639 struct rtsx_cr_option *option = &(pcr->option); in rts5250_set_l1off_cfg_sub_d0()
641 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5250_set_l1off_cfg_sub_d0()
646 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5250_set_l1off_cfg_sub_d0()
647 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5250_set_l1off_cfg_sub_d0()
660 if (rtsx_check_dev_flag(pcr, in rts5250_set_l1off_cfg_sub_d0()
668 rtsx_set_l1off_sub(pcr, val); in rts5250_set_l1off_cfg_sub_d0()
687 void rts524a_init_params(struct rtsx_pcr *pcr) in rts524a_init_params() argument
689 rts5249_init_params(pcr); in rts524a_init_params()
690 pcr->aspm_mode = ASPM_MODE_REG; in rts524a_init_params()
691 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); in rts524a_init_params()
692 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts524a_init_params()
693 pcr->option.ltr_l1off_snooze_sspwrgate = in rts524a_init_params()
696 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts524a_init_params()
697 pcr->ops = &rts524a_pcr_ops; in rts524a_init_params()
699 pcr->option.ocp_en = 1; in rts524a_init_params()
700 if (pcr->option.ocp_en) in rts524a_init_params()
701 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts524a_init_params()
702 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts524a_init_params()
703 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; in rts524a_init_params()
707 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) in rts525a_card_power_on() argument
709 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts525a_card_power_on()
711 return rtsx_base_card_power_on(pcr, card); in rts525a_card_power_on()
714 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts525a_switch_output_voltage() argument
718 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
720 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); in rts525a_switch_output_voltage()
723 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
725 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, in rts525a_switch_output_voltage()
732 rtsx_pci_init_cmd(pcr); in rts525a_switch_output_voltage()
733 rts5249_fill_driving(pcr, voltage); in rts525a_switch_output_voltage()
734 return rtsx_pci_send_cmd(pcr, 100); in rts525a_switch_output_voltage()
737 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) in rts525a_optimize_phy() argument
741 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts525a_optimize_phy()
746 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, in rts525a_optimize_phy()
751 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, in rts525a_optimize_phy()
755 if (is_version(pcr, 0x525A, IC_VER_A)) in rts525a_optimize_phy()
756 rtsx_pci_write_phy_register(pcr, _PHY_REV0, in rts525a_optimize_phy()
763 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) in rts525a_extra_init_hw() argument
765 rts5249_extra_init_hw(pcr); in rts525a_extra_init_hw()
767 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); in rts525a_extra_init_hw()
769 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts525a_extra_init_hw()
770 if (is_version(pcr, 0x525A, IC_VER_A)) { in rts525a_extra_init_hw()
771 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, in rts525a_extra_init_hw()
773 rtsx_pci_write_register(pcr, RREF_CFG, in rts525a_extra_init_hw()
775 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts525a_extra_init_hw()
777 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts525a_extra_init_hw()
779 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, in rts525a_extra_init_hw()
781 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, in rts525a_extra_init_hw()
783 rtsx_pci_write_register(pcr, OOBS_CONFIG, in rts525a_extra_init_hw()
804 void rts525a_init_params(struct rtsx_pcr *pcr) in rts525a_init_params() argument
806 rts5249_init_params(pcr); in rts525a_init_params()
807 pcr->aspm_mode = ASPM_MODE_REG; in rts525a_init_params()
808 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); in rts525a_init_params()
809 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts525a_init_params()
810 pcr->option.ltr_l1off_snooze_sspwrgate = in rts525a_init_params()
813 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts525a_init_params()
814 pcr->ops = &rts525a_pcr_ops; in rts525a_init_params()
816 pcr->option.ocp_en = 1; in rts525a_init_params()
817 if (pcr->option.ocp_en) in rts525a_init_params()
818 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; in rts525a_init_params()
819 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; in rts525a_init_params()
820 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; in rts525a_init_params()