Lines Matching refs:bp
22 #define BP_ILT(bp) NULL argument
26 #define BP_FUNC(bp) 0 argument
30 #define BP_PORT(bp) 0 argument
45 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
46 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
47 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
51 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, in bnx2x_init_str_wr() argument
57 REG_WR(bp, addr + i*4, data[i]); in bnx2x_init_str_wr()
60 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, in bnx2x_init_ind_wr() argument
66 bnx2x_reg_wr_ind(bp, addr + i*4, data[i]); in bnx2x_init_ind_wr()
69 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len, in bnx2x_write_big_buf() argument
72 if (bp->dmae_ready) in bnx2x_write_big_buf()
73 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); in bnx2x_write_big_buf()
76 else if (wb && CHIP_IS_E1(bp)) in bnx2x_write_big_buf()
77 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf()
81 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf()
84 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, in bnx2x_init_fill() argument
91 memset(GUNZIP_BUF(bp), (u8)fill, buf_len); in bnx2x_init_fill()
96 bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb); in bnx2x_init_fill()
100 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len) in bnx2x_write_big_buf_wb() argument
102 if (bp->dmae_ready) in bnx2x_write_big_buf_wb()
103 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len); in bnx2x_write_big_buf_wb()
106 else if (CHIP_IS_E1(bp)) in bnx2x_write_big_buf_wb()
107 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf_wb()
111 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len); in bnx2x_write_big_buf_wb()
114 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, in bnx2x_init_wr_64() argument
127 u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i; in bnx2x_init_wr_64()
135 bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len); in bnx2x_init_wr_64()
153 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, in bnx2x_sel_blob() argument
157 data = INIT_TSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
160 data = INIT_CSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
163 data = INIT_USEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
166 data = INIT_XSEM_INT_TABLE_DATA(bp); in bnx2x_sel_blob()
169 data = INIT_TSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
172 data = INIT_CSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
175 data = INIT_USEM_PRAM_DATA(bp); in bnx2x_sel_blob()
178 data = INIT_XSEM_PRAM_DATA(bp); in bnx2x_sel_blob()
183 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, in bnx2x_init_wr_wb() argument
186 if (bp->dmae_ready) in bnx2x_init_wr_wb()
187 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0); in bnx2x_init_wr_wb()
190 else if (CHIP_IS_E1(bp)) in bnx2x_init_wr_wb()
191 bnx2x_init_ind_wr(bp, addr, data, len); in bnx2x_init_wr_wb()
195 bnx2x_init_str_wr(bp, addr, data, len); in bnx2x_init_wr_wb()
198 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, in bnx2x_wr_64() argument
205 REG_WR_DMAE_LEN(bp, reg, wb_write, 2); in bnx2x_wr_64()
207 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, in bnx2x_init_wr_zp() argument
214 data = bnx2x_sel_blob(bp, addr, data) + blob_off*4; in bnx2x_init_wr_zp()
216 rc = bnx2x_gunzip(bp, data, len); in bnx2x_init_wr_zp()
221 len = GUNZIP_OUTLEN(bp); in bnx2x_init_wr_zp()
223 ((u32 *)GUNZIP_BUF(bp))[i] = (__force u32) in bnx2x_init_wr_zp()
224 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]); in bnx2x_init_wr_zp()
226 bnx2x_write_big_buf_wb(bp, addr, len); in bnx2x_init_wr_zp()
229 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) in bnx2x_init_block() argument
232 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, in bnx2x_init_block()
235 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, in bnx2x_init_block()
245 data_base = INIT_DATA(bp); in bnx2x_init_block()
249 op = (const union init_op *)&(INIT_OPS(bp)[op_idx]); in bnx2x_init_block()
262 REG_RD(bp, addr); in bnx2x_init_block()
265 REG_WR(bp, addr, op->write.val); in bnx2x_init_block()
268 bnx2x_init_str_wr(bp, addr, data, len); in bnx2x_init_block()
271 bnx2x_init_wr_wb(bp, addr, data, len); in bnx2x_init_block()
274 bnx2x_init_fill(bp, addr, 0, op->zero.len, 0); in bnx2x_init_block()
277 bnx2x_init_fill(bp, addr, 0, op->zero.len, 1); in bnx2x_init_block()
280 bnx2x_init_wr_zp(bp, addr, len, in bnx2x_init_block()
284 bnx2x_init_wr_64(bp, addr, data, len); in bnx2x_init_block()
290 if ((INIT_MODE_FLAGS(bp) & in bnx2x_init_block()
299 if ((INIT_MODE_FLAGS(bp) & in bnx2x_init_block()
475 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, in bnx2x_init_pxp_arb() argument
490 if (CHIP_REV_IS_FPGA(bp)) { in bnx2x_init_pxp_arb()
497 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); in bnx2x_init_pxp_arb()
498 REG_WR(bp, read_arb_addr[i].add, in bnx2x_init_pxp_arb()
500 REG_WR(bp, read_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
508 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
511 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
514 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
518 val = REG_RD(bp, write_arb_addr[i].l); in bnx2x_init_pxp_arb()
519 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
522 val = REG_RD(bp, write_arb_addr[i].add); in bnx2x_init_pxp_arb()
523 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
526 val = REG_RD(bp, write_arb_addr[i].ubound); in bnx2x_init_pxp_arb()
527 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
535 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); in bnx2x_init_pxp_arb()
540 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); in bnx2x_init_pxp_arb()
542 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); in bnx2x_init_pxp_arb()
543 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); in bnx2x_init_pxp_arb()
544 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); in bnx2x_init_pxp_arb()
545 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); in bnx2x_init_pxp_arb()
547 if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD)) in bnx2x_init_pxp_arb()
548 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); in bnx2x_init_pxp_arb()
550 if (CHIP_IS_E3(bp)) in bnx2x_init_pxp_arb()
551 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); in bnx2x_init_pxp_arb()
552 else if (CHIP_IS_E2(bp)) in bnx2x_init_pxp_arb()
553 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); in bnx2x_init_pxp_arb()
555 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); in bnx2x_init_pxp_arb()
557 if (!CHIP_IS_E1(bp)) { in bnx2x_init_pxp_arb()
564 if (!CHIP_IS_E1H(bp)) { in bnx2x_init_pxp_arb()
567 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val); in bnx2x_init_pxp_arb()
570 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); in bnx2x_init_pxp_arb()
573 REG_WR(bp, PXP2_REG_WR_HC_MPS, val); in bnx2x_init_pxp_arb()
574 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); in bnx2x_init_pxp_arb()
575 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); in bnx2x_init_pxp_arb()
576 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); in bnx2x_init_pxp_arb()
577 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); in bnx2x_init_pxp_arb()
578 REG_WR(bp, PXP2_REG_WR_QM_MPS, val); in bnx2x_init_pxp_arb()
579 REG_WR(bp, PXP2_REG_WR_TM_MPS, val); in bnx2x_init_pxp_arb()
580 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); in bnx2x_init_pxp_arb()
581 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); in bnx2x_init_pxp_arb()
582 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); in bnx2x_init_pxp_arb()
587 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST); in bnx2x_init_pxp_arb()
590 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20); in bnx2x_init_pxp_arb()
618 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, in bnx2x_ilt_line_mem_op() argument
633 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, in bnx2x_ilt_client_mem_op() argument
637 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_mem_op()
649 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i], in bnx2x_ilt_client_mem_op()
655 static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, u8 memop) in bnx2x_ilt_mem_op_cnic() argument
659 if (CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_mem_op_cnic()
660 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop); in bnx2x_ilt_mem_op_cnic()
662 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop); in bnx2x_ilt_mem_op_cnic()
667 static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop) in bnx2x_ilt_mem_op() argument
669 int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop); in bnx2x_ilt_mem_op()
671 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop); in bnx2x_ilt_mem_op()
672 if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_mem_op()
673 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop); in bnx2x_ilt_mem_op()
678 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx, in bnx2x_ilt_line_wr() argument
683 if (CHIP_IS_E1(bp)) in bnx2x_ilt_line_wr()
688 bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); in bnx2x_ilt_line_wr()
691 static void bnx2x_ilt_line_init_op(struct bnx2x *bp, in bnx2x_ilt_line_init_op() argument
702 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping); in bnx2x_ilt_line_init_op()
706 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping); in bnx2x_ilt_line_init_op()
711 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp, in bnx2x_ilt_boundry_init_op() argument
722 if (CHIP_IS_E1(bp)) { in bnx2x_ilt_boundry_init_op()
737 REG_WR(bp, start_reg + BP_FUNC(bp)*4, in bnx2x_ilt_boundry_init_op()
759 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start)); in bnx2x_ilt_boundry_init_op()
760 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end)); in bnx2x_ilt_boundry_init_op()
764 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp, in bnx2x_ilt_client_init_op_ilt() argument
775 bnx2x_ilt_line_init_op(bp, ilt, i, initop); in bnx2x_ilt_client_init_op_ilt()
778 bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop); in bnx2x_ilt_client_init_op_ilt()
781 static void bnx2x_ilt_client_init_op(struct bnx2x *bp, in bnx2x_ilt_client_init_op() argument
784 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_init_op()
786 bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop); in bnx2x_ilt_client_init_op()
789 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp, in bnx2x_ilt_client_id_init_op() argument
792 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_client_id_init_op()
795 bnx2x_ilt_client_init_op(bp, ilt_cli, initop); in bnx2x_ilt_client_id_init_op()
798 static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_op_cnic() argument
800 if (CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_init_op_cnic()
801 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop); in bnx2x_ilt_init_op_cnic()
802 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop); in bnx2x_ilt_init_op_cnic()
805 static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_op() argument
807 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop); in bnx2x_ilt_init_op()
808 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop); in bnx2x_ilt_init_op()
809 if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp)) in bnx2x_ilt_init_op()
810 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop); in bnx2x_ilt_init_op()
813 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num, in bnx2x_ilt_init_client_psz() argument
816 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_init_client_psz()
826 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12)); in bnx2x_ilt_init_client_psz()
837 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop) in bnx2x_ilt_init_page_size() argument
839 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU, in bnx2x_ilt_init_page_size()
841 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM, in bnx2x_ilt_init_page_size()
843 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC, in bnx2x_ilt_init_page_size()
845 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM, in bnx2x_ilt_init_page_size()
857 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_init_cid_count() argument
860 int port = BP_PORT(bp); in bnx2x_qm_init_cid_count()
867 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, in bnx2x_qm_init_cid_count()
876 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_set_ptr_table() argument
882 REG_WR(bp, base_reg + i*4, in bnx2x_qm_set_ptr_table()
884 bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2); in bnx2x_qm_set_ptr_table()
889 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count, in bnx2x_qm_init_ptr_table() argument
899 bnx2x_qm_set_ptr_table(bp, qm_cid_count, in bnx2x_qm_init_ptr_table()
901 if (CHIP_IS_E1H(bp)) in bnx2x_qm_init_ptr_table()
902 bnx2x_qm_set_ptr_table(bp, qm_cid_count, in bnx2x_qm_init_ptr_table()
915 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2, in bnx2x_src_init_t2() argument
919 int port = BP_PORT(bp); in bnx2x_src_init_t2()
927 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count); in bnx2x_src_init_t2()
929 bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16, in bnx2x_src_init_t2()
932 bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16, in bnx2x_src_init_t2()