1670 	u16 phy_reg;  in dmfe_set_phyxcer()  local
1678 		phy_reg = dmfe_phy_read(db->ioaddr,  in dmfe_set_phyxcer()
1682 			       db->phy_addr, 18, phy_reg, db->chip_id);  in dmfe_set_phyxcer()
1686 	phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;  in dmfe_set_phyxcer()
1690 		phy_reg |= db->PHY_reg4;  in dmfe_set_phyxcer()
1694 		case DMFE_10MHF: phy_reg |= 0x20; break;  in dmfe_set_phyxcer()
1695 		case DMFE_10MFD: phy_reg |= 0x40; break;  in dmfe_set_phyxcer()
1696 		case DMFE_100MHF: phy_reg |= 0x80; break;  in dmfe_set_phyxcer()
1697 		case DMFE_100MFD: phy_reg |= 0x100; break;  in dmfe_set_phyxcer()
1699 		if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;  in dmfe_set_phyxcer()
1703 	if ( !(phy_reg & 0x01e0)) {  in dmfe_set_phyxcer()
1704 		phy_reg|=db->PHY_reg4;  in dmfe_set_phyxcer()
1707 	dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);  in dmfe_set_phyxcer()
1726 	u16 phy_reg;  in dmfe_process_mode()  local
1745 		phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);  in dmfe_process_mode()
1746 		if ( !(phy_reg & 0x1) ) {  in dmfe_process_mode()
1748 			phy_reg = 0x0;  in dmfe_process_mode()
1750 			case DMFE_10MHF: phy_reg = 0x0; break;  in dmfe_process_mode()
1751 			case DMFE_10MFD: phy_reg = 0x100; break;  in dmfe_process_mode()
1752 			case DMFE_100MHF: phy_reg = 0x2000; break;  in dmfe_process_mode()
1753 			case DMFE_100MFD: phy_reg = 0x2100; break;  in dmfe_process_mode()
1756 				       db->phy_addr, 0, phy_reg, db->chip_id);  in dmfe_process_mode()
1760 				       db->phy_addr, 0, phy_reg, db->chip_id);  in dmfe_process_mode()
2040 	uint phy_reg;  in dmfe_program_DM9802()  local
2044 	phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);  in dmfe_program_DM9802()
2045 	phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;  in dmfe_program_DM9802()
2046 	dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);  in dmfe_program_DM9802()
2057 	uint phy_reg;  in dmfe_HPNA_remote_cmd_chk()  local
2060 	phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;  in dmfe_HPNA_remote_cmd_chk()
2061 	switch(phy_reg) {  in dmfe_HPNA_remote_cmd_chk()
2062 	case 0x00: phy_reg = 0x0a00;break; /* LP/LS */  in dmfe_HPNA_remote_cmd_chk()
2063 	case 0x20: phy_reg = 0x0900;break; /* LP/HS */  in dmfe_HPNA_remote_cmd_chk()
2064 	case 0x40: phy_reg = 0x0600;break; /* HP/LS */  in dmfe_HPNA_remote_cmd_chk()
2065 	case 0x60: phy_reg = 0x0500;break; /* HP/HS */  in dmfe_HPNA_remote_cmd_chk()
2069 	if ( phy_reg != (db->HPNA_command & 0x0f00) ) {  in dmfe_HPNA_remote_cmd_chk()