33 #define phy_write _phy_write  macro
63 	phy_write(phy, MII_BMCR, val);  in emac_mii_reset_phy()
74 		phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);  in emac_mii_reset_phy()
126 	phy_write(phy, MII_BMCR, ctl);  in genmii_setup_aneg()
146 	phy_write(phy, MII_ADVERTISE, adv);  in genmii_setup_aneg()
158 		phy_write(phy, MII_CTRL1000, adv);  in genmii_setup_aneg()
164 	phy_write(phy, MII_BMCR, ctl);  in genmii_setup_aneg()
184 	phy_write(phy, MII_BMCR, ctl | BMCR_RESET);  in genmii_setup_forced()
201 	phy_write(phy, MII_BMCR, ctl);  in genmii_setup_forced()
331 	phy_write(phy, MII_CIS8201_EPCR, epcr);  in cis8201_init()
334 	phy_write(phy, MII_CIS8201_ACSR,  in cis8201_init()
338 	phy_write(phy, MII_CIS8201_10BTCSR,  in cis8201_init()
370 	phy_write(phy, 0x14, 0x0ce3);  in m88e1111_init()
371 	phy_write(phy, 0x18, 0x4101);  in m88e1111_init()
372 	phy_write(phy, 0x09, 0x0e00);  in m88e1111_init()
373 	phy_write(phy, 0x04, 0x01e1);  in m88e1111_init()
374 	phy_write(phy, 0x00, 0x9140);  in m88e1111_init()
375 	phy_write(phy, 0x00, 0x1140);  in m88e1111_init()
393 	phy_write(phy, 0x16, 0x0002);  in m88e1112_init()
395 	phy_write(phy, 0x00, 0x0040); /* 1Gbps */  in m88e1112_init()
398 	phy_write(phy, 0x1a, reg_short);  in m88e1112_init()
402 	phy_write(phy, 0x16, 0x0000);  in m88e1112_init()
414 	phy_write(phy, 0x16, reg_short);  in et1011c_init()
418 	phy_write(phy, 0x17, reg_short);  in et1011c_init()
420 	phy_write(phy, 0x1c, 0x74f0);  in et1011c_init()
476 	phy_write(phy, 0x1d, 0x5); /* Address debug register 5 */  in ar8035_init()
477 	phy_write(phy, 0x1e, 0x2d47); /* Value copied from u-boot */  in ar8035_init()
478 	phy_write(phy, 0x1d, 0xb);    /* Address hib ctrl */  in ar8035_init()
479 	phy_write(phy, 0x1e, 0xbc20); /* Value copied from u-boot */  in ar8035_init()