Lines Matching refs:reg
23 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
28 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
29 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
31 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
33 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
35 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
37 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
39 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
46 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
49 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
51 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); in ixgbe_dcb_config_rx_arbiter_82598()
54 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_dcb_config_rx_arbiter_82598()
55 reg |= IXGBE_RDRXCTL_RDMTS_1_2; in ixgbe_dcb_config_rx_arbiter_82598()
56 reg |= IXGBE_RDRXCTL_MPBEN; in ixgbe_dcb_config_rx_arbiter_82598()
57 reg |= IXGBE_RDRXCTL_MCEN; in ixgbe_dcb_config_rx_arbiter_82598()
58 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
60 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_dcb_config_rx_arbiter_82598()
62 reg &= ~IXGBE_RXCTRL_DMBYPS; in ixgbe_dcb_config_rx_arbiter_82598()
63 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
84 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local
87 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); in ixgbe_dcb_config_tx_desc_arbiter_82598()
90 reg &= ~IXGBE_DPMCS_ARBDIS; in ixgbe_dcb_config_tx_desc_arbiter_82598()
91 reg |= IXGBE_DPMCS_TSOEF; in ixgbe_dcb_config_tx_desc_arbiter_82598()
94 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); in ixgbe_dcb_config_tx_desc_arbiter_82598()
96 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
101 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
102 reg |= refill[i]; in ixgbe_dcb_config_tx_desc_arbiter_82598()
103 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
106 reg |= IXGBE_TDTQ2TCCR_GSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
109 reg |= IXGBE_TDTQ2TCCR_LSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
111 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
133 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local
136 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); in ixgbe_dcb_config_tx_data_arbiter_82598()
138 reg &= ~IXGBE_PDPMCS_ARBDIS; in ixgbe_dcb_config_tx_data_arbiter_82598()
140 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); in ixgbe_dcb_config_tx_data_arbiter_82598()
142 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
146 reg = refill[i]; in ixgbe_dcb_config_tx_data_arbiter_82598()
147 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
148 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
151 reg |= IXGBE_TDPT2TCCR_GSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
154 reg |= IXGBE_TDPT2TCCR_LSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
156 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
160 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); in ixgbe_dcb_config_tx_data_arbiter_82598()
161 reg |= IXGBE_DTXCTL_ENDBUBD; in ixgbe_dcb_config_tx_data_arbiter_82598()
162 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
176 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local
180 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_pfc_82598()
181 reg &= ~IXGBE_RMCS_TFCE_802_3X; in ixgbe_dcb_config_pfc_82598()
182 reg |= IXGBE_RMCS_TFCE_PRIORITY; in ixgbe_dcb_config_pfc_82598()
183 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_pfc_82598()
186 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_dcb_config_pfc_82598()
187 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); in ixgbe_dcb_config_pfc_82598()
190 reg |= IXGBE_FCTRL_RPFCE; in ixgbe_dcb_config_pfc_82598()
192 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); in ixgbe_dcb_config_pfc_82598()
203 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
205 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); in ixgbe_dcb_config_pfc_82598()
209 reg = hw->fc.pause_time * 0x00010001; in ixgbe_dcb_config_pfc_82598()
211 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_dcb_config_pfc_82598()
229 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82598() local
235 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
236 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
237 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()
238 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); in ixgbe_dcb_config_tc_stats_82598()
239 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
240 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); in ixgbe_dcb_config_tc_stats_82598()
244 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
245 reg |= ((0x1010101) * i); in ixgbe_dcb_config_tc_stats_82598()
246 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()