Lines Matching refs:mtk_w32
60 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) in mtk_w32() function
77 mtk_w32(eth, val, reg); in mtk_m32()
106 mtk_w32(eth, PHY_IAC_ACCESS | in _mtk_mdio_write()
129 mtk_w32(eth, PHY_IAC_ACCESS | in _mtk_mdio_read()
190 mtk_w32(eth, TRGMII_MODE, INTF_MODE); in mtk_gmac0_rgmii_adjust()
200 mtk_w32(eth, val, INTF_MODE); in mtk_gmac0_rgmii_adjust()
213 mtk_w32(eth, val, TRGMII_RCK_CTRL); in mtk_gmac0_rgmii_adjust()
217 mtk_w32(eth, val, TRGMII_TCK_CTRL); in mtk_gmac0_rgmii_adjust()
290 mtk_w32(mac->hw, in mtk_mac_config()
371 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_mac_config()
433 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_down()
471 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); in mtk_mac_link_up()
620 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); in mtk_tx_irq_disable()
631 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); in mtk_tx_irq_enable()
642 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); in mtk_rx_irq_disable()
653 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); in mtk_rx_irq_enable()
672 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
674 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
678 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
680 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | in mtk_set_mac_address()
873 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); in mtk_init_fq_dma()
874 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); in mtk_init_fq_dma()
875 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); in mtk_init_fq_dma()
876 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); in mtk_init_fq_dma()
1109 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); in mtk_tx_map()
1113 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); in mtk_tx_map()
1267 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1273 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); in mtk_update_rx_cpu_idx()
1457 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); in mtk_poll_tx_qdma()
1542 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), in mtk_handle_status_irq()
1554 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); in mtk_napi_tx()
1586 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); in mtk_napi_rx()
1661 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); in mtk_tx_alloc()
1662 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); in mtk_tx_alloc()
1663 mtk_w32(eth, in mtk_tx_alloc()
1666 mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); in mtk_tx_alloc()
1667 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, in mtk_tx_alloc()
1670 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); in mtk_tx_alloc()
1671 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); in mtk_tx_alloc()
1672 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); in mtk_tx_alloc()
1673 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); in mtk_tx_alloc()
1780 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); in mtk_rx_alloc()
1781 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); in mtk_rx_alloc()
1782 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); in mtk_rx_alloc()
1783 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); in mtk_rx_alloc()
1841 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); in mtk_hwlro_rx_init()
1842 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); in mtk_hwlro_rx_init()
1843 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); in mtk_hwlro_rx_init()
1853 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); in mtk_hwlro_rx_init()
1856 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); in mtk_hwlro_rx_init()
1859 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, in mtk_hwlro_rx_init()
1871 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); in mtk_hwlro_rx_init()
1872 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_init()
1883 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_uninit()
1897 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); in mtk_hwlro_rx_uninit()
1900 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_uninit()
1910 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); in mtk_hwlro_val_ipaddr()
1912 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); in mtk_hwlro_val_ipaddr()
1915 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); in mtk_hwlro_val_ipaddr()
1925 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); in mtk_hwlro_inval_ipaddr()
1927 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); in mtk_hwlro_inval_ipaddr()
2152 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | in mtk_dma_init()
2154 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); in mtk_dma_init()
2267 mtk_w32(eth, in mtk_start_dma()
2274 mtk_w32(eth, in mtk_start_dma()
2279 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | in mtk_start_dma()
2308 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); in mtk_gdm_config()
2311 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); in mtk_gdm_config()
2312 mtk_w32(eth, 0, MTK_RST_GL); in mtk_gdm_config()
2366 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), in mtk_stop_dma()
2479 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); in mtk_dim_rx()
2481 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); in mtk_dim_rx()
2509 mtk_w32(eth, val, MTK_PDMA_DELAY_INT); in mtk_dim_tx()
2511 mtk_w32(eth, val, MTK_QDMA_DELAY_INT); in mtk_dim_tx()
2570 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); in mtk_hw_init()
2576 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); in mtk_hw_init()
2579 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); in mtk_hw_init()
2590 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); in mtk_hw_init()
2591 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); in mtk_hw_init()
2592 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); in mtk_hw_init()
2593 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); in mtk_hw_init()
2594 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); in mtk_hw_init()
2649 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); in mtk_change_mtu()