12 static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)  in ppe_w32()  argument
14 	writel(val, ppe->base + reg);  in ppe_w32()
17 static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)  in ppe_r32()  argument
19 	return readl(ppe->base + reg);  in ppe_r32()
22 static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)  in ppe_m32()  argument
26 	val = ppe_r32(ppe, reg);  in ppe_m32()
29 	ppe_w32(ppe, reg, val);  in ppe_m32()
34 static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)  in ppe_set()  argument
36 	return ppe_m32(ppe, reg, 0, val);  in ppe_set()
39 static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)  in ppe_clear()  argument
41 	return ppe_m32(ppe, reg, val, 0);  in ppe_clear()
44 static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)  in mtk_ppe_wait_busy()  argument
49 	ret = readl_poll_timeout(ppe->base + MTK_PPE_GLO_CFG, val,  in mtk_ppe_wait_busy()
54 		dev_err(ppe->dev, "PPE table busy");  in mtk_ppe_wait_busy()
59 static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)  in mtk_ppe_cache_clear()  argument
61 	ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);  in mtk_ppe_cache_clear()
62 	ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);  in mtk_ppe_cache_clear()
65 static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)  in mtk_ppe_cache_enable()  argument
67 	mtk_ppe_cache_clear(ppe);  in mtk_ppe_cache_enable()
69 	ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,  in mtk_ppe_cache_enable()
338 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,  in mtk_foe_entry_commit()  argument
349 	hwe = &ppe->foe_table[hash];  in mtk_foe_entry_commit()
364 	mtk_ppe_cache_clear(ppe);  in mtk_foe_entry_commit()
369 int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,  in mtk_ppe_init()  argument
377 	ppe->base = base;  in mtk_ppe_init()
378 	ppe->dev = dev;  in mtk_ppe_init()
379 	ppe->version = version;  in mtk_ppe_init()
381 	foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),  in mtk_ppe_init()
382 				  &ppe->foe_phys, GFP_KERNEL);  in mtk_ppe_init()
386 	ppe->foe_table = foe;  in mtk_ppe_init()
388 	mtk_ppe_debugfs_init(ppe);  in mtk_ppe_init()
393 static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)  in mtk_ppe_init_foe_table()  argument
398 	memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(*ppe->foe_table));  in mtk_ppe_init_foe_table()
406 			ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;  in mtk_ppe_init_foe_table()
409 int mtk_ppe_start(struct mtk_ppe *ppe)  in mtk_ppe_start()  argument
413 	mtk_ppe_init_foe_table(ppe);  in mtk_ppe_start()
414 	ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);  in mtk_ppe_start()
431 	ppe_w32(ppe, MTK_PPE_TB_CFG, val);  in mtk_ppe_start()
433 	ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,  in mtk_ppe_start()
436 	mtk_ppe_cache_enable(ppe, true);  in mtk_ppe_start()
448 	ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);  in mtk_ppe_start()
452 	ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);  in mtk_ppe_start()
456 	ppe_w32(ppe, MTK_PPE_BIND_AGE0, val);  in mtk_ppe_start()
460 	ppe_w32(ppe, MTK_PPE_BIND_AGE1, val);  in mtk_ppe_start()
463 	ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);  in mtk_ppe_start()
467 	ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);  in mtk_ppe_start()
471 	ppe_w32(ppe, MTK_PPE_BIND_RATE, val);  in mtk_ppe_start()
478 	ppe_w32(ppe, MTK_PPE_GLO_CFG, val);  in mtk_ppe_start()
480 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);  in mtk_ppe_start()
485 int mtk_ppe_stop(struct mtk_ppe *ppe)  in mtk_ppe_stop()  argument
491 		ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,  in mtk_ppe_stop()
494 	mtk_ppe_cache_enable(ppe, false);  in mtk_ppe_stop()
497 	ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);  in mtk_ppe_stop()
498 	ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);  in mtk_ppe_stop()
506 	ppe_clear(ppe, MTK_PPE_TB_CFG, val);  in mtk_ppe_stop()
508 	return mtk_ppe_wait_busy(ppe);  in mtk_ppe_stop()