Lines Matching refs:DESC_SIZE

394 #define DESC_SIZE	8		/* Should be cache line sized */  macro
464 			(4 * DESC_SIZE * dev->rx_info.next_rx),  in kick_rx()
523 	sg = dev->rx_info.descs + (next_empty * DESC_SIZE);  in ns83820_add_rx_skb()
534 …_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_em…  in ns83820_add_rx_skb()
595 	build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);  in clear_rx_desc()
834 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
836 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
915 		desc = info->descs + (DESC_SIZE * next_rx);
918 	info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
964 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1002 		desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1023 			__le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1033 	memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1125 	first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1128 		volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1134 		desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1455 		dev->tx_idx = txdp / (DESC_SIZE * 4);
1561 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1579 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1626 	memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1628 		dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1631 				  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1941 					   4 * DESC_SIZE * NR_TX_DESC,
1944 						4 * DESC_SIZE * NR_RX_DESC,
2187 	dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2189 	dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2211 	dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2213 	dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,