180 				  u32 *reg_space)  in _dwmac4_dump_dma_regs()  argument
182 	reg_space[DMA_CHAN_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
184 	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
186 	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =  in _dwmac4_dump_dma_regs()
188 	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
190 	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
192 	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
194 	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
196 	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =  in _dwmac4_dump_dma_regs()
198 	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =  in _dwmac4_dump_dma_regs()
200 	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =  in _dwmac4_dump_dma_regs()
202 	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =  in _dwmac4_dump_dma_regs()
204 	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =  in _dwmac4_dump_dma_regs()
206 	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =  in _dwmac4_dump_dma_regs()
208 	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =  in _dwmac4_dump_dma_regs()
210 	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
212 	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =  in _dwmac4_dump_dma_regs()
214 	reg_space[DMA_CHAN_STATUS(channel) / 4] =  in _dwmac4_dump_dma_regs()
218 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)  in dwmac4_dump_dma_regs()  argument
223 		_dwmac4_dump_dma_regs(ioaddr, i, reg_space);  in dwmac4_dump_dma_regs()